P. Radhika, Neelabh Tiwari, and Yogita Pant on ‘Design of Adder and Multiplier Using Quantum Dot Cellular Automata Based on Nanotechnology’, in ‘National Conference on Emerging Technology’ at ‘Anna University of Technology, Tirunelveli, India’ on 06-05-2011.

1. Design of Adder and Multiplier using Quantum
dot cellular automata based on Nanotechnology
P. RADHIKA NEELABH TIWARI YOGITA PANT
Asst. Prof., ECE Dept. M.Tech (VLSI-DESIGN), ECE Dept. Department of Physics
SRM UNIVERSITY SRM UNIVERSITY UNIVERSITY OF LUCKNOW
CHENNAI, INDIA CHENNAI, INDIA LUCKNOW, INDIA
gpradhika82@gmail.com neelabh1988@gmail.com yogita.idol@gmail.com
Abstract- Adders and multipliers are the basic building scaling down of CMOS devices. Quantum-dot
blocks of digital systems. Initially transistors are used to cellular automata is an emerging paradigm which
implement the circuit of adders and multipliers. Due to
the decreasing supply voltage, the power consumption allows operating frequencies in range of THz and
from leakage current is a big challenge for transistor device integration densities about 900 times more
circuits. Nanotechnology is the better alternative to than the current end of CMOS scaling limits, which
these problems. So in this project we will take help from
is not possible in current CMOS technologies.
nanotechnology to improve the design of adder and
multipliers. For doing this we use quantum dot Adders are fundamental circuits for most
automata which is an emerging nanotechnology. With digital systems. Better adder performance depends on
the potential for faster speed smaller size and lower minimizing the carry prorogation delay..
power consumption. Several adder and multiplier
designs in QCA have been proposed. Conventional Conventional adder circuits frequently require many
adder circuit requires many wires which are relatively wires which are relatively difficult to realize in QCA
difficult to realize in QCA technology. . That work technology. Due to these wire delays, most previous
demonstrated that the design trade-offs are very adder designs are limited in speed.
different in QCA. This paper utilizes the unique QCA
characteristics to design a carry flow adder that is fast Multiplier design has not been widely
and efficient. Simulations indicate very attractive considered by QCA designers. There is QCA
performance (i.e., complexity, area, and delay). multiplier design simplicity. Complex designs
generally incur long delays in QCA, so a simple
Keywords- Quantum-dot cellular automata, carry flow
adder, carry delay multiplier, 1-bit full adder. structure is a good choice for the starting point.
QCA designer is the product of an ongoing
I. Introduction effort to create a rapid and accurate simulation and
Quantum-dot cellular automata are an layout tool for quantum-dot cellular automata. QCA
emerging technology that offers a revolutionary designer is capable of simulating complex QCA
approach to computing at Nano-level. This circuits on most standard platforms.
technology has extra low power, high speed, and
extremely dense circuit. After decades of watching II. Quantum cellular automata
the Moore‟s law hold and enjoying the steady A. Cellular automata-
increase in transistor densities, the predominantly A cellular automaton is an abstract system
CMOS based Integrated Circuit industry now faces consisting uniform grid of cells. Each one of these
the prospect of transistor sizes hitting the physical cells can only be in one of a finite number of states at
limit. As sizes go well below the micro-scale, a discrete time. The state of each cell in this grid is
undesirable effects like high power dissipation and determined by the state of its adjacent cells, also
quantum-mechanical side-effects discourage further called the cell‟s neighborhood.
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2. B. Quantum cellular automata- within the cell. During the hold phase, the barriers are
Any device designed to represent data and kept high, which keeps the electrons highly localized
perform computation, regardless of the physics on two dots and giving the cell a set polarization.
principles it exploits and materials used to build it, This provides a driver cell for a neighbor. In the
must have two fundamental properties: distinguish release phase, the barriers are slowly reduced, which
ability and conditional change of state, the latter delocalizes the electrons, and the cell loses a distinct
implying the former. This means that such a device polarization value. The barriers in the relax phase are
must have barriers that make it possible to distinguish minimized, giving full freedom to the electrons and
between states, and that it must have the ability to preventing these cells from influencing neighbors.
control these barriers to perform conditional change During the switch phase, the barriers are slowly
of state. For example, in a digital electronic system, raised while the cells are driven by neighbors in the
transistor plays the role of such controllable energy hold phase. By the end of this phase, the cells are
barriers, making it extremely practical to perform distinctly polarized.
computing with them. The below fig1 (d) shows about the four
different clock zones available for the
C. Design of QCA cell- implementation of the logic circuits.
In quantum dot cellular automata, four
quantum dots occupy the corners of a square of the
cell with potential barriers between pair of dots.
Within this cell, two extra electrons are available, and
by raising and lowering the potential barriers with the
clock, an electron can localize on a dot. Due to
columbic interaction, these electrons will tend to Fig1 (d) QCA clock zones
occupy antipodal sites in the square cell. For an
isolated cell, there are two energetically equivalent Each of the clock signals is shifted in phase
arrangements of the extra electrons that are denoted by 90 degrees. This allows information to be pumped
as state polarization P. The cell polarization is used to through the circuit as a result of the successive
encode binary information. The basic building block latching and unlatching in cells attached to different
of QCA devices is the QCA cell shown in Figure clock cycles. These four clocking zones are
1(a). A polarization of P=+1 (Binary 0) results if cells implemented in QCA designer and each cell can be
1 and 3 occupied as in figure 1(b), while electrons on independently attached to anyone of the four clocking
sites 2 and 4 results in P=-1 (Binary 1) as shown in zones.
Figure 1(c). One of the main differences between circuit
design in QCA and circuit design using conventional
CMOS technologies and devices is that the circuit
has no control over the clocks. This means that
Fig1 (a) Basic QCA cell information is transmitted through each cell and not
retained.
III. QCA cell design
A. Signal flow and control-
Fig1 (b) Polarization= +1 Fig1 (c) Polarization= -1 A series of QCA cell acts like a wire. During
each clock cycle, half of the wire is active for signal
D. QCA clocking-
propagations, while the other half is stable. During
The clock used in QCA consists of four
the next clock cycle, half of the previous active zone
phases: hold, release, relax, and switch. Theses
is deactivated and the remaining active zone cells
phases correlate to action of the potential barriers
2

3. trigger the newly activated cells to be polarized. Thus D. Design rules-
signal propagates from one clock zone to the next. A nominal cell size of 20nm by 20nm is
assumed. The cell has a width and height of 18nm
and 5nm diameter quantum dots. The cells are placed
on a grid with a cell center to center distance of
Fig2 (a) QCA wire 20nm.
For circuit layout and functionality
B. QCA majority gate- checking, a simulation tool for QCA circuits, QCA
The majority gate implements logic function Designer is used. This tool allows users to do a
AB+BC+AC. The output cell assumes the custom layout and then verify QCA circuit
polarization of majority of three input cells. By functionality by simulations.
setting one of the majority gate inputs to logic „0‟ or
„1‟, the gate reduces to an AND or OR gate, IV. Adder design
respectively. A. Carry flow adder-
A 1. Basic design-
For fast calculation to reduce the carry
propagation delay. We add additional logic elements.
In Carry flow adder the path from carry-in to carry-
B M= (AB+BC+AC) out only uses one majority gate. The majority gate
always adds one more clock zone. Thus each bit in
the words to be added requires at least one clock zone
which sets the minimum delay.
C Sum = abcᵢ+abcᵢ bcᵢ bcᵢ
Fig2 (b) QCA majority gate
M c , M a, b, cᵢ), cᵢ)
Computation in a QCA majority gate is C = ab+bcᵢ+cᵢa
performed by driving the device cell to its lowest =M (a, b, cᵢ)
energy state. This is achieved when the device cell This is the equations for a full adder realized
assumes the polarization of the majority of the three with majority gates and inverters.
input cells.
2. Carry flow adder design-
C. QCA inverter- The schematic and layout are optimized to
The most common inverter design is shown minimize the delay and area. The carry propagation
in fig2 (c). This fork inverter has two legs of the delay for 1-bit is a quarter clocks and the delay from
input QCA wire which interact at 45° angle with the data inputs to the sum output is three quarter clocks.
first cell of the output wire. At this angle, the The wiring channels for the input/output
coupling between cells is negative and can be synchronization should be minimized since wire
exploited to realize the compliment function. channels add significantly to the circuit area.
A
B
Fig3 (a) Layout of 1-bit full adder
Fig2 (c) QCA inverter
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4. V. Multiplier design
A. FIR filter-
To consider the multiplication of two
numbers, start with a FIR filter. The FIR filter is
defined by equation.
Fig3 (b) Schematic of 1-bit full adder
Using the one cycle delay operator, Zˉ¹, the
Fig3 (a) and fig3 (b) show the layout and equation can be restated as
schematic diagram of 1-bit full adder. Fig3 (c) shows
the layout diagram of 4-bit carry flow adder.
Above equation can be implemented by the
network shown in fig4 (a).
Fig3 (c) Layout of 4-bit carry flow adder
B. Carry look ahead adder-
1. Basic design- Fig4 (a) FIR filter network
It is a type of adder used in digital logic. A
carry look ahead adder improves speed by reducing To use a pipeline design, both upper and
the amount of time required to determine carry bits. lower signal lines include the same additional delay
The carry look ahead adder calculates one or more units. Assume that Zˉ¼ is possible and apply the Zˉ½
carry bits before the sum, which reduces the wait delay element to each section with upper and lower
time to calculate the result of the larger value bits. lines. Below equation shows that fig4 (b) gives the
C M a, b, cᵢ) correct filter output result with N/2 cycle delay.
Sum= M (M , b, cᵢ), M a, b, cᵢ), M a, b, cᵢ)) Pipelined FIR filter output
2. Carry look ahead design-
The layout of carry look ahead adder is
shown in fig3 (d).
Fig3 (d) Layout of carry look ahead adder
Fig4 (b) Pipelined FIR filter
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5. B. Multiplication network-
Let (aᵢ, bᵢ) be the multiplicand and multiplier
pair and pᵢ be the product bit for position i. Bits aᵢ and
pᵢ correspond to words xᵢ and yᵢ of the filter. The
position i is the input at time i. Assume that the sum
generation takes at least Zˉ½ and the carry generation
Fig4 (g) CDM network for QCA
takes at least Zˉ¼. Even though fig4 c) and fig4 d)
ignored the zeroth full adder, the derivation includes
that adder. The implementation can be done as
Fig4 (h) Multiplier block diagram for CDM
Fig4 (c) Redirected FIR filter network Fig4 (g) is used for QCA circuit
implementation since it minimizes the latency from
the first input to the first output. Fig4 (h) shows the
block diagram of the optimized design for QCA
layout.
C. QCA implementation-
Fig4 (d) Pipelined redirected FIR filter network Bit-serial adders are used to realize the carry
delay multiplier. The bit- serial adder is modified
from the full adder so that carry-in and carry-out are
connected internally with a one clock delay.
Fig4 (i) and fig4 (j) shows the schematic and
layout diagram of 1-bit serial adder.
This is denoted as a carry delay multiplier
(CDM). It is optimized to minimize the latency of the
output. The carry delay multiplier minimizes the
latency to the output.
Fig4 (i) Schematic diagram of 1-bit serial adder
Fig4 (k) and fig4 (l) shows the layout and
simulation of carry delay multiplier.
Fig4 (e) Carry delay multiplication
Fig4 (j) Layout of 1-bit serial adder
Fig4 (f) Redirected FIR filter network for QCA
5

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VII. References
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and Multiplier Design in Quantum-Dot Cellular
6