SiConTech provides end-to-end Chip Design and product development services to Fabless semiconductor companies and Electronic OEMs worldwide for multiple target markets including Consumer, Storage, Wireless, Automotive, Defense & Aerospace and Industrial applications. Along with its ecosystem partners, SiConTech is a one-stop-shop place for your complete Chip Design needs. Founded in 2010, with a strong engineering workforce of over 700 engineers with extensive IC development skillsets, SiConTech is able to quickly build, scale and deliver ahead of time under challenging schedules. SiConTech is headquartered in Bengaluru, India with development and sales offices in Hyderabad, Santa Clara-CA, Austin-TX, China, Israel and support locations worldwide. SiConTech can provide services in the following flexible business models: • Onsite Engineering extensions or independent teams • Offshore development center • Turnkey, Time & Material delivery • Resource Augmentation • Hybrid model/ Co-managed model

1. SiConTech Design TechnologiesYour End To End ASIC Design Partner
Presenting: Our Digital Library Expertise
For Higher Speed, Lower Power and Smaller Area…this is our expertise.

2. Standard Cell Design Expertise
SiConTech Library Expertise
Switches
Isolation Cells
Level Shifters
Retention Flops
Always on Buffers
Combinatorial
Sequential
Low Power Cells
Special Cells
Complex Booleans
Multiplexers
Adders
Best Performance
Lowest Power
Technology Nodes
Flops
Latches
Ultra High Performance
Low Power Versions
Vector/Multibit
Lowest Area
Test LSSD, unbufferedinput flops
Typical Requirement
Lowest Area
Synchronizers
SER Flops
Clock Gates
Clock Buffers
Delay Cells for DLL etc.,
28nm
45nm
65nm
90nm
130nm
1500 Cells
20-100 Corner Characterization
Multi VT
Multi-Height
Co-optimization Layout/Parasitic/Design

3. Library Expertise (1)
•Technologies : 130nm, 90nm, 65nm, 45nm, 28nm, 20nm
•Process definition & Technology Entitlement w/ Foundries
–DRC rule deck analysis
–Iterative development with Backend and Frontend teams
•Library Architecture Definition for best PPPAS
–PPPAS evaluation through actual synthesis/P&R evaluation on target design blocks
–Multiple What-IFs for track heights to determine best in class
•Performance/area benefits
•Power bus structures
•Power management requirement
–Routabilityanalysis for optimum place and route of library in real design scenario
–Cell composition evaluation and definition based on PPPAS requirements
•Cell design
–Combinatorial, complex booleans, flavoursof multiplexers, adders
–Sequential cells including flops, latches, ultra high performance, low power versions
–Flop architectures to meet ultra low power targets such as vector and multibit
–Non traditional sequentialsto meet performance or test requirements such as LSSD, unbufferedinput flops
–Power management portfolio (switches, level shifters, retention flops, isolation cells)
–Special cells such as synchronizer, SER flops, clock gates, clock buffers etc
Confidential

4. Library Expertise (2)
•Layouts
–Best in class density-can reach 50% of Area Reduction compared to STD library.
–Best in class performance with parasitic and design and layout co-optimization
–Proven methods of automation to increase efficiency by several X
•Quality
–Silicon proven methods of robustness checks on designs through statistical simulation and analysis
–Automated library QC and delivery methods to ensure validity, completeness and consistency of all views
–Usage of library on target design to validate PPPA requirements as well as tool compatibility
–Experience in silicon debug and analysis of actual product issues related to core cells
•Library Complexity per technology node
–1500 base cells, mutipleVT flavours, multiple cell heights
–Characterization of 20-100PTVs
–Handled several asynchronous release requests from design teams
–Aggressive targets for all design teams to meet schedules met 95% or more of the times
Confidential

5. Library Projects Highlights
•Architected and developed an Ultra-High Density Library on TSMC 28LP node
–Architecture, cell-design, layouts and timing checks
–Including base-library and power-management kit
•Layout development on TSMC 20/16FF towards a high performance library
–Layouts and physical verification; quick turn-around times
–Re-char of existing library with new process models and cell addition for speed
–Layouts, characterization, views generation, thorough QA, release
•Benchmarking vendor libraries on 40 and 28nm nodes
–Analysis at cell-level and block-level
–Customer design taken through synthesis , P&R and speed/power/delay/routing metrics collected
•Addition of low-powercells to an existing base library targeting 30% lower dynamic power
–Cell-design, layout, characterization, design-level analysis, feedback and complete QA/Release

6. Would you like to Squeeze more out of your Silicon?
Contact Us For In-Depth Technical Discussion
Yossi Yehiel
International BD and Sales
Email: Yossi.yehiel@sicontech.com
Phone:+972-54-8027273