AJ

Arun Joseph

14 Slideshow
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A Distributed Co-Simulation Environment and its Application in HW-FW Verification
porArun Joseph
 
IBM_NEXA_DAC2021 NEXA, a cloud-native platform for collaborative hardware logic design
porArun Joseph
 
DVCON24-IBM ai/ml driven hardware verification
porArun Joseph
 
LabReplay_DAC2021 LabReplay, a post-silicon hardware debug flow that creates an "expanded" set of debug data in a simpler Normalized (NMZ) model of high-performance microprocessor designs
porArun Joseph
 
Rapidly Building Next Generation Web-based EDA Applications and Platforms from Legacy Tools
porArun Joseph
 
Techniques for Efficient RTL Clock and Memory Gating Takedown of Next Generation High-performance Microprocessor Designs
porArun Joseph
 
FVCAG: A framework for formal verification driven power modelling and verification
porArun Joseph
 
FreqLeak
porArun Joseph
 
Process synchronization in multi core systems using on-chip memories
porArun Joseph
 
FirmLeak
porArun Joseph
 
A Hybrid Approach to Standard Cell Power Characterization based on PVT Independent Contributor Modeling for use in Traditional Power Analysis Flows
porArun Joseph
 
Empirically Derived Abstractions in Uncore Power Modeling for a Server-Class Processor Chip
porArun Joseph
 
End to End Self-Heating Analysis Methodology and Toolset for High Performance Microprocessor Designs
porArun Joseph
 
Per domain power analysis
porArun Joseph