![Power: The Metric For Chip Success ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Power dissipated = voltage X current Current Drawn](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
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- 1. Comprehensive Low Power Design Analysis and Optimization An RTL to GDSII Approach Aveek Sarkar and Ronen Stilkol Apache Design Solutions
- 5. Power in the RTL GDS II Flow Target power reduction early in the design flow Ensure design verification to predict voltage drop noise from low power techniques Power reduction Usage Curve Power Integrity Usage Curve Physical Implementation & Signoff RTL Design & reduction Floor-planning & Synthesis Chip-Package-System Convergence
- 7. Operational Power Reduction Clock Tree Optimization RTL: Add and Improve Clock Enables Non-enabled Enabled sel sel_1d 1 R2 D RTL reductions make clock gating more effective EN CLK CG GCLK D EN CLK D Synthesis: Clock Gating RTL Gates
- 8. Operational Power Reduction Datapath Optimization
- 11. Impact of Design and Process Changes on Silicon Integrity
- 15. Chip Package System Convergence An RTL to GDSII Focus 06/22/10 , RTL to GDS CPS Convergence RTL Design & reduction RTL Power Reduction RTL Power Analysis Floor-planning & Synthesis PG, IO Planning Early CPM Package/PCB planning Physical Implementation & Signoff IP Validation SoC Analysis Timing Impact CPS sign-off + cost down