1. “ Design, Analysis and Simulations of a Si Schottky Diode Based Sampling Circuit for 40 Gbps ETDM Demultiplexer Circuit “ Supervisors: Prof. Dr. techn. Peter Russer Jung Han Choi, M.S. Master Thesis: Septiaji Eko Nugroho Master of Science in Microwave Engineering (MSMWE) Program Institute for High Frequency Engineering

5. The Demultiplexer Circuit for ETDM system The Demultiplexer Circuit for ETDM system 1. Sampling Circuit for Demultiplexer Diagram of 4-Way Demultiplexer Diagram of Optical Receiver

6. The Sampling Theory and The Undersampling Technique for Demultiplexer (1) 1. Sampling Circuit for Demultiplexer

7. The Sampling Theory and The Undersampling Technique for Demultiplexer (2) Input : Ideal NRZ signal NRZ pulse: Output of the first channel: is “1” or “0” 1. Sampling Circuit for Demultiplexer

8. The Sampling Theory and The Undersampling Technique for Demultiplexer (3) For 1:2 Demultiplexer: Output of the first channel: Output of the second channel: (Undersampling Technique) 1. Sampling Circuit for Demultiplexer

9. The Sampling Theory and The Undersampling Technique for Demultiplexer (4) Output 1. Sampling Circuit for Demultiplexer

13. Driving Requirements 2. Circuit Requirements and Components Broadband Characteristic is Important Circuit bandwidth > 40 GHz is necessary Spectrum of 40 Gbps NRZ signal PRBS 2 7 -1

16. DC Characteristic of the Diode Model 2. Circuit Requirements and Components We define turn-on point of the diode is 480 mV

17. Flip-Chip Bonding AuSn (1) 2. Circuit Requirements and Components Equivalent Model Resonance frequency *): *)Chun-Long Wang and Ruey-Beei Wu, “A Locally matching Technique for Broadband Flip-chip Transition Design,” IEEE Trans. Microwave Theory Tech. , pp. 1399, February 2002 . Using L=103 pH, C=45 fF, Zo=50 Ohm f res =76.9 GHz Height= 5 um Diameter=50 um

18. Flip-Chip Bonding AuSn (2) 2. Circuit Requirements and Components Equivalent Model*) The double diode pad C=20 fF *) Jung Han Choi, C.-J. Weiske, G.R. Olbrich, P. Russer, “Flip-chip bonded Si Schottky Sampling Circuits for High Speed Demultiplexer”, Microwave Symposium Digest, 2003 IEEE MTT-S International , vol. 3, pp. 1515-1518, 8-13 June 2003.

21. Basic Operation : Turning On the Diode (1) Proper operation Turn-on point = 480 mV 3. Design, Analysis and Simulation

23. Simulation Results Input 40 Gbps PRBS 2 7 -1 Output Channel 1 Output Channel 2 3. Design, Analysis and Simulation

26. Bandwidth Optimization (2) - Analytic Transfer function: Define : 3. Design, Analysis and Simulation

27. Bandwidth Optimization (3) - Analytic Transfer function: It has low pass characteristic, with cutoff frequency: or 3. Design, Analysis and Simulation

28. Bandwidth Optimization (4) – S-Parameter Simulation 3. Design, Analysis and Simulation

30. Bandwidth Optimization (6) – Comparison 3. Design, Analysis and Simulation

34. Layout Design (4)-SC_0110 1000 um x 1400 um. Distance betwen capacitor and diode is 250 um 3. Design, Analysis and Simulation

35. Layout Design (5)-SC_0110 55 GHz bandwidth with linear phase is achieved using Chold 0.1 pF. ADS Co-simulation Result: 3. Design, Analysis and Simulation

37. Operation in Lower Speed 20 Gbps DEMUX 1:2 Chold=0.35 pF 10 Gbps DEMUX 1:2 Chold=0.65 pF 3. Design, Analysis and Simulation

38. Flip-Chip Bonding Effect (1) 3. Design, Analysis and Simulation

39. Flip-Chip Bonding Effect (2)-40 Gbps Input Without flipchip With flipchip 3. Design, Analysis and Simulation

40. Flip-Chip Bonding Effect (3)-86 Gbps Input Without flipchip With flipchip Input 86 Gbps RZ PRBS 2 7 -1 Output Eyewaveform Flip-chip bonding highly affects the 86 Gbps performance. 3. Design, Analysis and Simulation

42. Effect of Asymmetry: Oscillator Phase Difference (2) 10 o phase difference 5 o phase difference 15 o phase difference Up to 5 o difference can be tolerated 3. Design, Analysis and Simulation

47. Thank You! Vielen Dank! Terimakasih! Maturnuwun! Syukron!