ASIC DESIGN OF MINI-STEREO DIGITAL AUDIO PROCESSOR UNDER SMIC 180NM TECHNOLOGY DESIGNED A 350NM TWO STAGE OPERATIONAL AMPLIFIER
DESIGNED DYNAMIC SEGMENTED LRU AND MODIFIED MOESI PROTOCOL FOR RING CONNECTED FILTER CACHES USING GEM5
PARASITIC-AWARE FULL PHYSICAL CHIP DESIGN OF LNA RFIC AT 2.45GHZ USING IBM 130NM TECHNOLOGY
RELIABLE NoC ROUTER ARCHITECTURE DESIGN USING IBM 130NM TECHNOLOGY
ACCURATE Q-PREDICTION FOR RFIC SPIRAL INDUCTORS USING THE 3DB BANDWIDTH
PARASITICS REDUCTION FOR RFIC CMOS LAYOUT AND IIP3 VS Q-BASED DESIGN ANALYSIS USING IBM 130NM TECHNOLOGY
STANDARD CELL LIBRARY DESIGN
