This paper presents the design and performance comparison of a two stage operational amplifier topology using CMOS and BiCMOS technology. This conventional op amp circuit was designed by using RF model of BSIM3V3 in 0.6 μm CMOS technology and 0.35 μm BiCMOS technology. Both the op amp circuits were designed and simulated, analyzed and performance parameters are compared. The performance parameters such as gain, phase margin, CMRR, PSRR, power consumption etc achieved are compared. Finally, we conclude the suitability of CMOS technology over BiCMOS technology for low power RF design.

1. Design and Performance Analysis of Low Power RF
Operational Amplifier using CMOS and BiCMOS
Technology
A. Baishya1
, Trupa Sarkar2
, P. P. Sahu1
and M. K. Naskar3
1
Dept of ECE, Tezpur University, Assam, India.
Email: anukul@tezu.ernet.in.
2
GDC Kamalpur, Dept of ETCE, Tripura, India.
Email: trupa.sarkar@gmail.com.
3
Dept of ETCE, Jadavpur University, Kolkata, India
Abstract— This paper presents the design and performance comparison of a two stage
operational amplifier topology using CMOS and BiCMOS technology. This conventional op
amp circuit was designed by using RF model of BSIM3V3 in 0.6 µm CMOS technology and
0.35 µm BiCMOS technology. Both the op amp circuits were designed and simulated,
analyzed and performance parameters are compared. The performance parameters such as
gain, phase margin, CMRR, PSRR, power consumption etc achieved are compared. Finally,
we conclude the suitability of CMOS technology over BiCMOS technology for low power
RF design.
Index Terms— RF CMOS, frequency response, unity gain, unity gain bandwidth, gain
margin, phase margin.
I. INTRODUCTION
The growing demand in low power and at the same time high performance design plays an important role and
creates a challenging task in modern analog and mixed signal systems that are expected to operate at low
supply voltages. Many low power applications require high performance op amp which is considered to be
one of the most widely used circuit blocks. To design an op amp with wide input common mode range at low
supply voltage, complementary differential pairs are usually required and the minimum supply voltage in this
case is given by 4ܸ஽௦௔௧ + ்ܸே + |்ܸ௉|. Potentially increasing requirement for reduced cost, less chip area,
reduced power consumption and improved performance demand integration of mixed signal systems on the
same die. Effort towards integration of this versatile circuit block started way back in 1960 [1], the µA 709
being the first integrated op amp.
The power supply requirement for digital circuits is less compared to analog circuits and can be achieved by
voltage scaling. Since threshold voltage (்ܸு) does not scale down at the same rate as (ܸௗௗ), it results in
reduced common mode range, output swing and linearity of the op amp. As the supply voltage decreases, it
becomes increasingly challenging to maintain the transistors in saturation [2]. Therefore, the designers need
to opt for low power design techniques to integrate analog circuit blocks along with digital circuits on a
single chip using standard CMOS technology. Operational amplifiers based on CMOS technology with
different levels of complexity are used to understand functions like dc bias generation, high speed
DOI: 02.ITC.2014.5.72
© Association of Computer Electronics and Electrical Engineers, 2014
Proc. of Int. Conf. on Recent Trends in Information, Telecommunication and Computing, ITC

2. 130
amplification, high output swing and reasonable open loop unity gain bandwidth (UGB) product. With the
increase in cut off frequency as technology shrinks to sub-micrometer range, CMOS technology has been in
the run from its counterpart bipolar technology.
The optimum trade-off among die area, power consumption and operating speed of an op amp can be
achieved when the transistors are operated in their moderate inversion region of operation [3], [4]. Amplifiers
designed to operate at radio frequency differs from conventional low frequency circuit design approaches and
demand special considerations [5], [6]. In RF regime, stability analysis becomes an important issue with
noise and gain figures. The key parameters associated with an RF op amp are gain (dB), operating frequency
and bandwidth (Hz), output power (dBm), power supply requirement, input and output refection coefficients
(VSWR), noise figure (dB) etc. Transistors are mainly used in RF op amps as gain elements. An overview of
CMOS op amp design is described in [7].
II. DESIGN OF A TWO STAGE OP AMP
The op amp architecture employed in this work comprises of two stages as shown in fig 1. The first stage is a
differential stage with an active load which is used to amplify the differential input voltage suppressing the
common mode voltage. The input differential amplifier stage is designed to achieve high input impedance,
large CMRR, and PSRR, low offset voltage, low noise and high gain. The second stage is an inverting output
stage. Additional differential stage is used in order to enhance the gain of the op amp. The circuit was
designed with RF models of BSIM3v3 MOSFET with a supply voltage obtained from the I – V
characteristics shown in fig 2 and fig 3 obtained by simulating the NMOS and PMOS transistors. During the
simulation of the CMOS and BiCMOS op amps supply voltages were so chosen that both the transistors
operate in their moderate inversion region resulting in optimum power supply requirement.
The two stage op amp circuit shown in fig 1 was designed using PMOS and NMOS devices derived from RF
models of BSIM3v3 [8] made available by AWR Microwave office version 9.05. As seen in the figure, the
differential stage comprises of transistors M1 to M4. M1 and M2 are NMOS transistors while M3 and M4 are
PMOS transistors.
This differential stage forms the basic stage of the op amp. A differential input signal applied across the two
input terminals will be amplified according to the gain of the differential stage. The current mirror active load
formed using M3 and M4 performs the differential to single ended conversion of the input signal. Transistor
M13 acts as a current source supply and with M12, supplies a voltage between the gate and the source of M5,
M7 and M9. Transistor M5 acts as a simple current source while M7 serves as a load for the driver M6,
which form the second gain stage. It also acts as a level shifter. The source follower consists of the transistors
M10 and M11. M10 acts as a driver and M11 acts as a load. Parallel connected channels of the
complementary transistors M10 and M11 form a resistance ‘R’ which is used as a compensation technique
for improvement of phase margin. The resistance is connected to the input of second stage gain to the output
and hence acts as a feedback.
A. CMOS and BiCMOS implementation
The two stage opamp shown in fig 1 employs PMOS and NMOS devices those were derived using 0.6 µm
CMOS and 0.35 µm BiCMOS process parameters. The devices were simulated for V-I characteristics in
order to obtain the supply voltage required for operating them in moderate inversion region. The simulation
results for V-I characteristics of PMOS and NMOS devices are shown in fig 2 and fig 3 respectively.
III. SIMULATION RESULTS
The two stage op amp circuit of fig 1 was simulated using the PMOS and NMOS devices derived above in
0.6 µm CMOS and 0.35 µm BiCMOS technology and were simulated for gain, phase margin, CMRR and
PSRR. The simulation results obtained for these parameters for the CMOS and BiCMOS circuits are
described below.
A. Frequency response
The frequency response obtained by simulating the op amp circuit of fig 1 in CMOS and BiCMOS
technology are shown in fig 4 and fig 5 respectively. It is observed that a gain of 22.69dB and a phase margin
of 450
is achieved for the CMOS op amp while BiCMOS op amp provides a gain of 12dB with a phase
margin of 600
. The unity gain bandwidth (UGB) of the CMOS and the BiCMOS op amp were found to be
11.2 GHz and 4.2 GHz respectively.

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Fig. 1 Two stage Op amp circuit diagram
Fig 2. V-I Characteristics of PMOS device

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Fig 3. V-I Characteristics of NMOS device
Fig 4. Frequency response of CMOS op amp
Fig 5. Frequency response of BiCMOS op amp
B. Common mode rejection ratio (CMRR)
The op amp circuit was simulated for CMRR in Microwave office version 9.05. The CMRR in dB was
obtained by applying two identical voltage sources in series with the op amp inputs and employing a unity
gain feedback. CMRR of 80 dB and 26 dB as seen in fig 6 and fig 7 were obtained for CMOS and BiCMOS
implementation respectively.

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Fig 6. CMRR of CMOS op amp
Fig 7. CMRR of BiCMOS op amp
Fig. 8. PSRR of CMOS op amp
C. Power supply rejection ratio (PSRR)
The power supply rejection ratio (PSRR) of the CMOS and BiCMOS implementations of the proposed op
amp architecture were obtained by simulating the circuit with inputs shorted in unity gain configuration. The
values obtained for PSRR (+) and PSRR(-) of the CMOS op amp are 30 dB and 60 dB respectively as shown
in fig 8 while the PSRR(+) and PSRR(-) of the BiCMOS op amp were obtained as 42 dB and 22 dB
respectively as shown in fig 9.
D. Device geometry and electrical yields
The device geometry of the NMOS and PMOS devices employed in constructing the op amp circuit in
CMOS and BiCMOS technologies are shown in TABLE I and TABLE II respectively along with the
electrical parameters yielded. The device dimensions were arrived at through repeated simulation and
optimization.

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Fig 9. PSRR of BiCMOS op amp
TABLE I. DEVICE GEOMETRY AND PERFORMANCE PARAMETERS OF CMOS OP AMP
DESIGN PARAMETERS ELECTRICAL
PARAMETERS YIELDED
M1, M2 W/L=42.2;
L=0.6
Phase Margin 44°
M3,M4 W=25; L=0.6 UGB 11.31
GHz
M5 W=33.1; L=1.2 DC Gain 22.69dB
M6 W=9; L=0.6 PSRR(+ve) 30dB
M7 W=5.84; L=1.2 PSRR(-ve) 60dB
M8 W=0.6; L=0.6 CMRR 80dB
M9 W=0.6; L=1.2 Power
Consumption
83.8mW
M10, M11 W=6.7; L=0.6 Slew Rate 39.21V/ns
M12 W=6; L=0.6
M13 W=3.9; L=0.6
VDD 0.8V
CL 1fF
IREF 1.5mA
TABLE II. DEVICE GEOMETRY AND PERFORMANCE PARAMETERS OF BICMOS OP AMP
THE DESIGN PARAMETERS THE ELECTRICAL PARAMETERS YIELDED
M1, M2 W=18; L=0.35 Phase Margin 60°
M3,M4 W=9; L=0.35 Unity Gain Frequency 4.2 GHz
M5 W=21; L=0.35 DC Gain 12dB
M6 W=15; L=0.35 PSRR(+ve) 42dB
M7 W=18; L=0.35 PSRR(-ve) 23dB
M8 W=18; L=0.35 CMRR 26dB
M9 W=12; L=0.35 Power Consumption 133mW
M10 W=10; L=0.6 Slew Rate 18.22V/ns
M11 W=9; L=0.6
VDD 3.5V
CL 1fF
IREF 3.1mA

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TABLE III. PERFORMANCE COMPARISON OF CMOS AND BICMOS OPAMP
The performance parameter as obtained by simulating and optimizing the op amp implemented in CMOS and
BiCMOS technology are tabulated as shown in TABLE III. It is observed that the CMOS implementation of
the two stage op amp outperforms the BiCMOS implementation.
IV. CONCLUSION
The most commonly used two stage op amp topology was used to perform a comparative study using 0.6 µm
and 0.35 µm BiCMOS process technology. It was observed that the CMOS implementation of the same
circuit topology outperforms the BiCMOS implementation almost in all aspects and thereby revalidates the
suitability of CMOS technology for low power RF analog circuit design.
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OPAMP
PARAMETER
OPAMP USING
GenBic35
OPAMP USING
BSIM3v3
Phase Margin 60° 44°
Unity Gain
Frequency
4.2 GHz 11.31
DC Gain 12dB 22.69dB
PSRR(+ve) 42dB 30.1
PSRR(-ve) 23dB 60.3
CMRR 26dB 80
Power
Consumption
133mW 83.8
Slew Rate 18.22V/ns 39.21