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Low power high_speed
1. LOW POWER HIGH
SPEED MULTIPLIERS
Submitted by:
K.NAVYA (09C81AO456)
B.BHANU PRASAD (09C81AO416)
B.SUVARNA KUMARI(09C81AO426)
A.GANDHI (09C81A0401)
2. INTRODUCTION
Booth’s multiplication algorithm was invented by
ANDREW BOOTH in 1951
This algorithm is particularly useful for machines that
can shift bits faster than adding them.
Another improvement in the multiplier is by reducing the
number of partial products generated.
It operates even with signed numbers
3.
4. BRAUN ARRAY MULTIPLIER
braun edward louis first proposed the braun
multiplier in 1963.
it is a simple parallel multiplier that is commonly
known as the carry array multiplier.
This is restricted to performing multiplication of two
unsigned numbers.
It consists of an array of and gates and adders
arranged in an iterative structure that does not require
logic registers.
This is also known as the non-additive multiplier
since it does not add an additional operand to the
result of the multiplication.
6. An n*n –bit braun multiplier requires n(n-1) adders
and n2 and gates .
The internal structure of the full adder used in the
braun multiplier makes braun multipliers ideal for
very large scale integration (vlsi) and application
specific integrated circuit (asic) realization.
each of the xiyj product bits is generated in
parallel with the and gates.
Each partial product can be added to the previous
sum of partial products by using adders.
The carry out signals are shifted one bit to the left
and are then added to the sums of the first adder
and the new partial product.
8. PERFORMANCE :
The braun multiplier performs well for
unsigned operands that are less than 16 bits, in
terms of speed, power and area.
Besides, it has a simple and regular structure as
compared to the other multiplier schemes.
How ever, the number of components required
in building the braun multiplier increases
quadratically with the number of bits.
This makes the braun multiplier inefficient and
so it is rarely employed while handling large
operands.
9. SPEED CONSIDERATION:
The delay of the braun multiplier i is dependent on the
delay of the full adder cell and also on the final adder
in the last row.
In the multiplier array, a full adder with balanced
carry and sum delays is desirable because the sum and
carry signals are both in the critical path.
The speed and power of the full adder is very
important for large arrays.
10. BOOTH’S MULTIPLIER
A multiplier has two stages.
In the first stage, the partial products are
generated by the booth encoder and the
partial product generator (ppg), and are
summed by compressors.
In the second stage, the two final products
are added to form the final product
through a final adder.
14. OPERATION OF BOOTH
MULTIPLIER
The booth encoder was implemented using two xor
gates and the selector using 3muxes and an inverter
careful optimization of the partial-product generation
can lead to some substantial delay and hardware
reduction.
[8] in the normal 8*8 multiplication 8 partial products
need to be generated and accumulated.
For accumulation seven adders to reduce power are
required but in the case of booth
17. ADVANTAGES
Booth multiplier operates with high speed
It has low complexity
Low power consumption
It has less access time
18. APPLICATIONS:
It is arithmetic operation for dsp
applications.
Such as ‘filtering ‘, and for fourier
transforms.
To achieve high execution speed, parallel
array multipliers are widely used .
These multipliers tend to consume most
of power in dsp computions
19. COMPARISON:
ARRAY MULTIPLIER BOOTH S MULTIPLIER
1.Total power consumption is 1.Total power consumption is
267mW. 263mW.
2.Time period is 13.553 nsec. 2.Time period is 2.52 nsec.
3.It has more complexity. 3.It has less complexity.
20. SUMMARY AND
CONCLUSION
the braun array multiplier and booth
multiplier was implemented using vhdl
and the results are verified for the braun
and booth multipliers.
