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IQxplorer MIPS 64-bit processors Project – MSCS 521 Computer Architecture MANAN SHAH ( Block Diagram & its detailed explanation, Instruction set) CHINTAN SHIHORA (Overview, Features, Intro to 64-bit processing , pipelining information , Pros & Cons)
OVERVIEW
Overview ,[object Object],[object Object]
Overview (cont.) ,[object Object],[object Object]
INTRODUCTION TO 64 BIT PROCESSOR
[object Object],[object Object],What 64-bit refers to?
Need of 64-bit processor ,[object Object],[object Object]
FEATURES OF MIPS 64-bit processors
Features: ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Features: (cont.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Features: (cont.)
INSTRUCTION SET FOR MIPS 64-bit processors
MIPS 64-bit processors Instructions:
BLOCK DIAGRAM FOR MIPS 64-bit processors
Block Diagram: It supports four floating-point multiply-add/subtract instructions which allow two separate floating-point computations to be performed with one instruction. The four instructions are : 1. Multiply-add (MADD) 2. Multiply-subtract (MSUB) 3. Negative Multiply-add (NMADD) 4. Negative Multiply-Subtract (NMSUB)
Index : 1 ) Large On-chip Caches 2) Dual Entry TLB 3) Write Buffer 4) Pipelining 5) Dual-Issue Mechanism 6) Dedicated Integer and FP ALU’s 7) Separate FP Execution Units 8) Scaleable for Multiple Processors 9) Secondary Cache Support 10) Multiple Cache Sizes 11) Simultaneous Access 12) Flexible Clocking Mechanism 13) On-chip Clock Multiplication Circuitry Detailed Explanation (For Block Diagram)
[object Object],[object Object],[object Object],[object Object],[object Object],Large on- chip Caches: (Detailed explanation- Block diagram)
[object Object],[object Object],Large on- chip Caches: (cont.) (Detailed explanation- Block diagram)
[object Object],[object Object],[object Object],[object Object],Dual Entry TLB: (Detailed explanation- Block diagram)
[object Object],[object Object],[object Object],[object Object],Write Buffer: (Detailed explanation- Block diagram)
[object Object],[object Object],[object Object],[object Object],Write Buffer: (cont.) (Detailed explanation- Block diagram)
[object Object],[object Object],[object Object],[object Object],Pipelined Writes: (Detailed explanation- Block diagram)
[object Object],[object Object],[object Object],[object Object],[object Object],Pipelining : (Detailed explanation- Block diagram) A non-pipelined execution Pipelined execution
Pipelining (cont.) ,[object Object],[object Object],[object Object]
Parallel Pipelining ,[object Object],[object Object],[object Object]
SuperPipeline ,[object Object],[object Object],[object Object]
SuperScalar Pipeline ,[object Object]
How Pipelining Works: ,[object Object],[object Object],[object Object]
How Pipelining Works: (cont.) ,[object Object],[object Object],[object Object],[object Object],[object Object]
How Pipelining Works: (cont.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Floating point Co-processor: ,[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],Dual Issue Mechanism: (Detailed explanation- Block diagram)
[object Object],[object Object],[object Object],Dedicated Integer & FP ALU: (Detailed explanation- Block diagram)
[object Object],[object Object],[object Object],Scalable for Multiple processor: (Detailed explanation- Block diagram)
[object Object],[object Object],Separate FP Execution Units: (Detailed explanation- Block diagram)
[object Object],[object Object],[object Object],[object Object],[object Object],Secondary Cache Support: (Detailed explanation- Block diagram)
[object Object],[object Object],[object Object],[object Object],Multiple Cache Sizes: (Detailed explanation- Block diagram)
[object Object],[object Object],Simultaneous Access: (Detailed explanation- Block diagram)
[object Object],[object Object],[object Object],[object Object],Flexible Clocking Mechanism: (Detailed explanation- Block diagram)
[object Object],[object Object],[object Object],On Chip Clock Multiplication Circuitry: (Detailed explanation- Block diagram)
PROS & CONS
Advantages: ,[object Object],[object Object],[object Object]
Disadvantages: ,[object Object],[object Object]
References: ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

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Mips 64

  • 1. IQxplorer MIPS 64-bit processors Project – MSCS 521 Computer Architecture MANAN SHAH ( Block Diagram & its detailed explanation, Instruction set) CHINTAN SHIHORA (Overview, Features, Intro to 64-bit processing , pipelining information , Pros & Cons)
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  • 5. INTRODUCTION TO 64 BIT PROCESSOR
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  • 8. FEATURES OF MIPS 64-bit processors
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  • 12. INSTRUCTION SET FOR MIPS 64-bit processors
  • 13. MIPS 64-bit processors Instructions:
  • 14. BLOCK DIAGRAM FOR MIPS 64-bit processors
  • 15. Block Diagram: It supports four floating-point multiply-add/subtract instructions which allow two separate floating-point computations to be performed with one instruction. The four instructions are : 1. Multiply-add (MADD) 2. Multiply-subtract (MSUB) 3. Negative Multiply-add (NMADD) 4. Negative Multiply-Subtract (NMSUB)
  • 16. Index : 1 ) Large On-chip Caches 2) Dual Entry TLB 3) Write Buffer 4) Pipelining 5) Dual-Issue Mechanism 6) Dedicated Integer and FP ALU’s 7) Separate FP Execution Units 8) Scaleable for Multiple Processors 9) Secondary Cache Support 10) Multiple Cache Sizes 11) Simultaneous Access 12) Flexible Clocking Mechanism 13) On-chip Clock Multiplication Circuitry Detailed Explanation (For Block Diagram)
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