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“ Modeling System behaviors ”….A better Paradigm on prototyping -Nilesh Ranpura
Electronic System Structure Hardware development process Software development process System development process Software input/output Hardware input/output Abstraction trade offs
System Abstraction and Development Process ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],SPI 5 Design Flow Concept Chip/Block specs Product Specs System data/environment Board/proto specs Architecture specs Not  documented Reference Platforms Hardware  and  proto specs
Which are those System Properties ? Environmental System Properties Hardware & Software co-exist Safety/ Standards/ Compliance Performance New  Approaches : Green mode  Error injection Mixed Signal
Compute Blade PCIe Inter-Domain Switch I/O Hub CPU CPU Memory Memory Memory Memory Local Storage Processor SATA / SAS Expander Dual GbE Controller Dual GbE Controller I/O Blade Processor Compute Blade PCIe Inter-Domain Switch I/O Hub CPU CPU Memory Memory Memory Memory (1)PCIe Switch Applications – System Interconnect Processor FC FC Fibre Channel  Controller Storage Blade PCIe  System Interconnect  Switch GbE GbE GbE GbE Compute Blade I/O Hub CPU CPU Memory Memory Memory Memory
Model parameter Values ECRC, etc Misc. Testcase 20/100/500/5000 No of packets Testcase 2/4/5/6/8 Active Port Testbench PM or non PM State Testcase 2.5Ghz, 5Ghz Speed Testbench Multicast, One to one, Many to one Traffic pattern Testcase MRD,MWR,IRD Packet types Testcase 128/256/512 Payload Testbench 128 MPS Remark Value Parameter
Model Latency definition ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],97% 3.360 3.459 128 95% 2.905 3.048 64 81% 2.000 2.462 32 Switch efficiency (Actual/Theoretical) % Actual throughput (GBps) Theoretical(GBps) Payload (Bytes)
Usage  Model and Error Model I/O CPU NTB P2P P2P P2P P2P P2P NTB I/O I/O I/O I/O CPU NTB P2P P2P P2P P2P P2P NTB I/O I/O I/O ... Internal Switch Error I/O 1GbE PCIe Switch I/O Hub CPU Memory ... I/O 1GbE I/O 1GbE PCIe Switch I/O Hub CPU Memory ... ... I/O 1GbE External Error
(2)Modeling Channel properties and Mixed signal for Simple Link ,[object Object],[object Object],[object Object],[object Object]
(2)Introduce Digital Noise ,[object Object],[object Object],[object Object],[object Object],[object Object],Noise Model 22 20 15 5 4 3 8 bit value of 20(sample value) ,[object Object],[object Object],[object Object],Noise Model
(2)Actual System High speed PHY  MAC  PAM modulation and Signal path  processing block
(2)Actual System ,[object Object],[object Object],[object Object],[object Object],High speed PHY  MAC  PAM modulation and Signal path  processing block  ,[object Object],[object Object],[object Object],Noise Model
Thank You,  All…!

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Nilesh ranpura systemmodelling

  • 1. “ Modeling System behaviors ”….A better Paradigm on prototyping -Nilesh Ranpura
  • 2. Electronic System Structure Hardware development process Software development process System development process Software input/output Hardware input/output Abstraction trade offs
  • 3.
  • 4. Which are those System Properties ? Environmental System Properties Hardware & Software co-exist Safety/ Standards/ Compliance Performance New Approaches : Green mode Error injection Mixed Signal
  • 5. Compute Blade PCIe Inter-Domain Switch I/O Hub CPU CPU Memory Memory Memory Memory Local Storage Processor SATA / SAS Expander Dual GbE Controller Dual GbE Controller I/O Blade Processor Compute Blade PCIe Inter-Domain Switch I/O Hub CPU CPU Memory Memory Memory Memory (1)PCIe Switch Applications – System Interconnect Processor FC FC Fibre Channel Controller Storage Blade PCIe System Interconnect Switch GbE GbE GbE GbE Compute Blade I/O Hub CPU CPU Memory Memory Memory Memory
  • 6. Model parameter Values ECRC, etc Misc. Testcase 20/100/500/5000 No of packets Testcase 2/4/5/6/8 Active Port Testbench PM or non PM State Testcase 2.5Ghz, 5Ghz Speed Testbench Multicast, One to one, Many to one Traffic pattern Testcase MRD,MWR,IRD Packet types Testcase 128/256/512 Payload Testbench 128 MPS Remark Value Parameter
  • 7.
  • 8. Usage Model and Error Model I/O CPU NTB P2P P2P P2P P2P P2P NTB I/O I/O I/O I/O CPU NTB P2P P2P P2P P2P P2P NTB I/O I/O I/O ... Internal Switch Error I/O 1GbE PCIe Switch I/O Hub CPU Memory ... I/O 1GbE I/O 1GbE PCIe Switch I/O Hub CPU Memory ... ... I/O 1GbE External Error
  • 9.
  • 10.
  • 11. (2)Actual System High speed PHY MAC PAM modulation and Signal path processing block
  • 12.
  • 13. Thank You, All…!

Notas del editor

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