Personal Information
Organización/Lugar de trabajo
Thiruvananthapuram India
Ocupación
Scientist
Sector
Government / Military
Sitio web
http://www.cdacb.in
Acerca de
I am working in VLSI field. Main areas of work is FPGA and ASIC based system design.
Major research areas include :-
Computer architecture,
Reversible computing
Quantum computing
Vedic mathematics
Network on chip,
Application Specific integrated circuit(ASIP)
Main focus on research oriented development for INDIA
Etiquetas
processor design
microprocessor
micro controller
processor
fpga
vhdl
branch prediction
ip core
mips
computer architecture
pipeline stalls
pipe lining idealism
uart
transistors
analog design
electronic circuits
universal asynchronous receive and transmit
serial communication
rs 232
instruction set
control hazard
data hazard
tcl
modelsim
reversible logic gates
fredkin gate
feynman gate
not gate
toffolli gate
reversible computing
aligned memory access
unaligned memory access
memory access
external fragmentation
internal fragmentation
pipe lining
superscalar
l1 cache
arm
fpu
neon
arm cortex-a8
rs232
ieee 802.15.1 protocol
system on chip
bluetooth on fpga
soc
bluetooth
refcomm
alu
arithmetic and logic unit
fetch module
asic
decoder
execute
cisc
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Presentaciones
(4)Documentos
(6)Personal Information
Organización/Lugar de trabajo
Thiruvananthapuram India
Ocupación
Scientist
Sector
Government / Military
Sitio web
http://www.cdacb.in
Acerca de
I am working in VLSI field. Main areas of work is FPGA and ASIC based system design.
Major research areas include :-
Computer architecture,
Reversible computing
Quantum computing
Vedic mathematics
Network on chip,
Application Specific integrated circuit(ASIP)
Main focus on research oriented development for INDIA
Etiquetas
processor design
microprocessor
micro controller
processor
fpga
vhdl
branch prediction
ip core
mips
computer architecture
pipeline stalls
pipe lining idealism
uart
transistors
analog design
electronic circuits
universal asynchronous receive and transmit
serial communication
rs 232
instruction set
control hazard
data hazard
tcl
modelsim
reversible logic gates
fredkin gate
feynman gate
not gate
toffolli gate
reversible computing
aligned memory access
unaligned memory access
memory access
external fragmentation
internal fragmentation
pipe lining
superscalar
l1 cache
arm
fpu
neon
arm cortex-a8
rs232
ieee 802.15.1 protocol
system on chip
bluetooth on fpga
soc
bluetooth
refcomm
alu
arithmetic and logic unit
fetch module
asic
decoder
execute
cisc
Ver más