The document provides an overview of ARM processor architectures. It discusses ARM's range of RISC processor core designs including early processors like ARM7TDMI and ARM9TDMI. It covers the evolution of architectures like ARMv6, ARMv7, and ARMv7-M. It provides details on Cortex processor families like Cortex-A, Cortex-R, and Cortex-M. It describes features of various Cortex processors including pipeline stages, memory systems, and instruction sets. The document is intended to introduce the reader to ARM architectures and processor families.
2. AGENDA
• Introduction to ARM and the Architecture
Processor Families
Programmer’s Model
AAETC2v00
Architecture 2
Programmer’s Model
Exceptions and Interrupts
3. ARM LTD
• ARM founded in November 1990
– Advanced RISC Machines
• Company headquarters in Cambridge, UK
– Processor design centers in Cambridge, Austin, and Sophia
Antipolis
– Sales, support, and engineering offices all over the world
• Best known for its range of RISC processor cores designs
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Architecture 3
• Best known for its range of RISC processor cores designs
– Other products – fabric IP, software tools, models, cell libraries -
to help partners develop and ship ARM-based SoCs
• ARM does not manufacture silicon
• More information about ARM and our offices on their
web site:
– http://www.arm.com/aboutarm/
4. On chip
EXAMPLE ARM-BASED SYSTEM
• ARM core deeply embedded within an
SoC
– External debug and trace via JTAG or
CoreSight interface
• Design can have both external and
internal memories
– Varying width, speed and size –
depending on system requirements
ARM
Processor
core
AMBAAXI
External
Memory
Interface
DMA
Port
Clocks and
Reset Controller
DEBUG
nIRQ
nFIQ
FLASH
SDRAM
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Architecture 4
memory
depending on system requirements
• Can include ARM licensed CoreLink
peripherals
– Interrupt controller, since core only
has two interrupt sources
– Other peripherals and interfaces
• Can include on-chip memory from
ARM Artisan Physical IP Libraries
• Elements connected using AMBA
(Advanced Microcontroller Bus
Architecture)
APB
Bridge
AMBAAPB
CoreLink
Interrupt
Controller
Other
CoreLink
Peripherals
nFIQ
ARM based
SoC
Custom
Peripherals
9. ARCHITECTURE ARMV7 PROFILES
• Application profile (ARMv7-A)
– Memory management support (MMU)
– Highest performance at low power
• Influenced by multi-tasking OS system requirements
– TrustZone and Jazelle-RCT for a safe, extensible system
– e.g. Cortex-A5, Cortex-A9
• Real-time profile (ARMv7-R)
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Architecture 9
• Real-time profile (ARMv7-R)
– Protected memory (MPU)
– Low latency and predictability ‘real-time’ needs
– Evolutionary path for traditional embedded business
– e.g. Cortex-R4
• Microcontroller profile (ARMv7-M, ARMv7E-M, ARMv6-M)
– Lowest gate count entry point
– Deterministic and predictable behavior a key priority
– Deeply embedded use
– e.g. Cortex-M3
10. TRUSTZONE SECURITY EXTENSIONS
• Extensions added for ARM1176, and for all V7-A cores
• Application is divided into “Secure” and “Non-Secure” worlds
• New “Secure Monitor” exception mode
• Secure Monitor exception handling code acts as a gatekeeper for moving between
worlds.
• Separate exception tables for secure and non secure worlds
• Memory (on-chip, caches, and TCMS) can be marked for secure access only
• Debug for secure world code and data restricted
Secure WorldNormal World System Boot
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Architecture 10
Secure World
Secure
Kernel
Normal World
Secure
Monitor
Secure service
Platform
OS
User mode
Privileged mode
User mode
Privileged mode
Process
11. LPAE
• The Large Physical Address Extensions (LPAE) is an optional extension to
ARMv7-A
– Supported by Cortex-A15 and Cortex-A7
• LPAE provides:
– New translation table format - Long-descriptor Format
– 32-bit virtual addresses, with 40-bit physical address
– Can still use (existing) Short-descriptor page table format
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Architecture 11
– Can still use (existing) Short-descriptor page table format
32-bit virtual address space
40-bit physical address space
• New Privileged Execute Never (PXN) attribute
• New hierarchical attributes (XNTable, PXNTable, NSTable and APTable)
12. ARMV7-A VIRTUALIZATION
EXTENSIONS
• ARMv7-A has an optional virtualization extension
– Implemented by the Cortex-A15 and Cortex-A7
• Provides hardware support for “full” virtualization
– In the Normal world only, no virtualization support in the Secure world
Secure worldNormal world
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Architecture 12
Guest OS
Hypervisor
Trusted OS
Trusted Service(s)
Secure Monitor
Application(s)
Guest OS
Application(s)PL0
PL1
PL2
14. AGENDA
Introduction to ARM and the Architecture
• Processor Families
Programmer’s Model
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Architecture 14
Programmer’s Model
Exceptions and Interrupts
15. ARM7TDMI PROCESSOR
• 3-stage pipeline
• on Neumann architecture
– Single instruction and data
memory interface
• T D M I =
T Thumb instruction set support
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Architecture 15
D Debug support
M Enhanced multiplier (32x8) with
instructions for 64-bit results
I Embedded ICE Logic
• ARM7TDMI-S - synthesizable
version of the ARM7TDMI
– Instruction Set and Cycle
compatible with ARM7TDMI
Hard Macrocell
– Single Clock Design (rising edge)
– Simplified Bus Interface
16. ARM9TDMI PROCESSOR FAMILY
• 5-stage pipeline
– Improved maximum clock frequency
• Harvard architecture
– Separate instruction and data
interface
– Simultaneous instruction and data
access
• Normally supplied with caches
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Architecture 16
• Normally supplied with caches
attached
• ARM920T
– 2 x 16K caches
– Memory Management Unit (MMU)
– Write Buffer
• ARM922T (pictured)
– Same as ARM922T but with 2 x 8K
caches
• ARM940T
– Memory Protection Unit (MPU)
17. ARM926EJ-S PROCESSOR
• Based on the ARM9-E core
• 5-stage pipeline (similar to ARM9TDMI)
• Configurable Instruction and Data
caches
• Configurable Instruction and Data
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Architecture 17
• Configurable Instruction and Data
TCMs
• AHB bus interface
• Memory Management Unit
• Jazelle DBX support
– Can execute some Java bytecodes in
hardware
18. ARM1176JZ(F)-S PROCESSOR
• ARM1176JZ(F)-S
– Architecture v6Z - TrustZone
– 8-stage pipeline
• Load/Store Unit separate
from ALU
• Static and dynamic branch
prediction
– Physically-tagged 4-64k caches
– Dual configurable TCMs
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Architecture 18
– Dual configurable TCMs
– Memory management unit
– Four AXI memory ports
– Jazelle-DBX support
– Optional integrated VFP
coprocessor
• ARM1136J(F)-S (not shown here)
– AHB memory interface
– No TrustZone support
– Single TCMs
19. ARM1156T2(F)-S PROCESSOR
• ARM1156T2(F)-S
– Architecture v6T2 – Thumb-2
support
• Core can run completely in
Thumb state (including
exceptions)
– 9-stage pipeline
• Load/Store Unit separate
from ALU
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Architecture 19
from ALU
• Static and dynamic branch
prediction
– Physically-tagged 4-64k caches
– Configurable TCMs
– Memory protection unit
– Three AXI memory ports
– Optional integrated vectored
interrupt controller port
– Optional integrated VFP
coprocessor
20. ARM11 MPCORE PROCESSOR
• Up to 4 ARMv6K processors
• Snoop Control Unit
– Maintains L1 D-cache coherency
• Integrated distributed Interrupt
Controller (GIC)
• 1 or 2 external AMBA3 AXI master
interfaces
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Architecture 20
• Each CPU features
– Private timer and watchdog
– MMU
– 16, 32 or 64K L1 caches
• 4-way set-associative
• Write-back, write-allocate
– Optional VFP
– JTAG based debug
21. CORTEX-A8
• ARMv7-A Architecture
– Thumb-2
– Thumb-2EE (Jazelle-RCT)
– TrustZone extensions
• Custom or synthesized design
• MMU
• 64-bit or 128-bit AXI Interface
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Architecture 21
• 64-bit or 128-bit AXI Interface
• L1 caches
– 16 or 32KB each
• Unified L2 cache
– 0-2MB in size
– 8-way set-associative
• Optional features
• VFPv3 Vector Floating-Point
• NEON media processing engine
• Dual-issue, super-scalar 13-stage pipeline
• Branch Prediction & Return Stack
• NEON and VFP implemented at end of pipeline
22. CORTEX-A9 MPCORE
• ARMv7-A Architecture
– ARM, Thumb-2, Thumb-2EE
– TrustZone support
• Snoop Control Unit
– Maintains L1 Data cache coherency between
processors
– Arbitrates accesses to the L2 memory system
– Optional Accelerator Coherency Port
Cluster of up to 4 Cortex-A9
processors
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Architecture 22
– Optional Accelerator Coherency Port
• Integrated Interrupt Controller (GIC)
• Variable-length Multi-issue pipeline
• 64-bit AXI instruction and data interfaces
• L1 Data and Instruction caches
– 16-64KB each
– 4-way set-associative
• Single-core version does not have integrated
interrupt controller
– Supports standard interface for PL390 GIC
• Optional features
• PTM instruction trace interface
• IEM power saving support
• Full Jazelle DBX support
• VFPv3-D16 Floating-Point Unit (FPU)
or NEON™ media processing engine
23. CORTEX-A5 MPCORE
• ARMv7-A Architecture
– ARM, Thumb-2, Thumb-2EE
– TrustZone support
• Snoop Control Unit
– Maintains L1 Data cache coherency between
processors
– Arbitrates accesses to the L2 memory system
Cluster of up to 4 Cortex-A5
processors
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Architecture 23
– Arbitrates accesses to the L2 memory system
– Optional Accelerator Coherency Port
• Integrated Interrupt Controller (GIC)
– Not integrated in single-core configuration
• 64-bit AXI instruction and data interfaces
• L1 Data and Instruction caches
– 4-64KB each
– 4-way set-associative
• Optional features
• PTM instruction trace interface
• IEM power saving support
• Full Jazelle DBX support
• VFPv3-D16 Floating-Point Unit (FPU)
or NEON™ media processing engine
24. CORTEX-A15 MPCORE
• 1-4 processors per cluster
• Fixed size L1 caches (32KB)
• Integrated L2 Cache
– 512KB – 4MB
• System-wide coherency support with
AMBA 4 ACE
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Architecture 24
AMBA 4 ACE
• Backward-compatible with
AXI3 interconnect
• Integrated Interrupt Controller
– 0-224 external interrupts for entire cluster
• CoreSight debug
• Advanced Power Management
• Large Physical Address Extensions (LPAE) to ARMv7-A Architecture
• Virtualization Extensions to ARMv7-A Architecture
25. CORTEX-A7 MPCORE
• Architecturally identical to Cortex-A15
• Smaller, lower power and performance
than Cortex-A15
• 1-4 processors per cluster
• Optional integrated L2 Cache
• System-wide coherency support with
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Architecture 25
• System-wide coherency support with
AMBA 4 ACE
• Backward-compatible with
AXI3 interconnect
• Optional integrated Interrupt Controller
• CoreSight debug
• Advanced Power Management
• Architectural changes:
• Large Physical Address Extensions (LPAE)
• Virtualization Extensions
27. CORTEX-R5
• ARMv7-R Architecture
– Divide instructions
– Support for mixed endianness
– Unaligned data support
• Optional FPU
• High Performance Core
– 8-stage dual-issue pipeline
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Architecture 27
– 8-stage dual-issue pipeline
– Program flow prediction
• L1 memory system
– Caches and TCMs
– Low latency peripheral ports
– Parity and ECC support
– Accelerator coherency port
• Optional second CPU
– Twin CPU or redundant CPU
28. ARMV7-M OVERVIEW
• Register and ISA changes
– Same register numbers, but only one set of general purpose registers
– Thumb-2 only - no ARM instruction set support
– No CPSR - use different set of status registers
• Different processor modes and exception model
– Only two modes - Thread mode and Handler mode (each with their own stack
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Architecture 28
– Only two modes - Thread mode and Handler mode (each with their own stack
pointer)
– Vector table contains addresses, not instructions
– Interrupts automatically save/restore state (r0-r3, r12, lr)
– Exception handlers can be completely programmed in C
• No coprocessor 15 (system control coprocessor)
– All control registers are memory-mapped
• Fixed memory map for external memory
– No cache, no MMU
29. CORTEX-M3
• ARMv7-M Architecture
• Thumb-2 only
• Fully programmable in C
• 3-stage pipeline
• von Neumann architecture
• Optional MPU
• AHB-Lite bus interface
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Architecture 29
Cortex M3 Total
60k* Gates
• AHB-Lite bus interface
• Fixed memory map
• 1-240 interrupts
• Configurable priority levels
• Non-Maskable Interrupt support
• Debug and Sleep control
• Serial wire or JTAG debug
• Optional ETM
30. CORTEX-M4
• ARMv7E-M Architecture
• Thumb-2 only
• DSP extensions
• Optional FPU (Cortex-M4F)
• Otherwise, same as Cortex-M3
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Architecture 30
Cortex M3 Total
60k* Gates
• Implements full Thumb-2
instruction set
• Saturated math (e.g. QADD)
• Packing and unpacking (e.g. UXTB)
• Signed multiply (e.g. SMULTB)
• SIMD (e.g. ADD8)
31. CORTEX-M0
• ARMv6-M Architecture
• 16-bit Thumb-2 with system control
instructions
• Fully programmable in C
• 3-stage pipeline
• von Neuman architecture
• AHB-Lite bus interface
• Fixed memory map
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Architecture 31
Cortex M3 Total
60k* Gates
• Fixed memory map
• 1-32 interrupts
• Configurable priority levels
• Non-Maskable Interrupt support
• Low power support
• Core configured with or without
debug
• Variable number of watchpoints and
breakpoints
32. CORTEX-M0+
• ARMv6-M Architecture
• Fully programmable in C
• 2-stage pipeline
• Optional MPU
• Optional User/Privilege support
• AHB-Lite bus interface
• Relocatable vector table
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Architecture 32
•
• Optional system timer
• Optional debug support
• 1-32 interrupts
• Configurable priority levels
• Non-Maskable Interrupt support
• Low power support
• Single-cycle I/O portMost power-efficient ARM
processor to date!
33. SECURCORE - SC100, SC200, SC300
• The first secure 32-bit RISC
processor
• Intended for use in smart cards and
other secure embedded applications
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Architecture 33
• Secure design based on existing
ARM core designs (ARM7, Cortex-
M3)
– Synthesizable, fully static design
– Secure Memory Protection Unit
– Thumb support for code density
– Specific and unique anti-
counterfeiting design features
– Small and power-efficient
34. AGENDA
Introduction to ARM and the Architecture
Processor Families
• Programmer’s Model
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Architecture 34
• Programmer’s Model
Exceptions and Interrupts
35. ARM PROCESSOR MODES
Mode Description
Supervisor
(SVC)
Entered on reset and when a Supervisor call instruction
(SVC) is executed
FIQ Entered when a high priority (fast) interrupt is raised
IRQ Entered when a normal priority interrupt is raised
Exceptionmodes
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Architecture 35
Privileged
modes
Abort Used to handle memory access violations
Undef Used to handle undefined instructions
Hyp Used for hardware virtualization support
Monitor Used for TrustZone secure monitor program
System Privileged mode using the same registers as User mode
User Mode under which most Applications / OS tasks run
Unprivileged
mode
Exceptionmodes
Cortex-A15/A7only
Same
registerbank
37. REGISTER SET BEHAVIOR ON
EXCEPTIONS
User moder0
r1
r2
r3
r4
r5
r6
r7
r8 r8
FIQ mode r0
r1
r2
r3
r4
r5
r6
r7
r8 r8
Registers in use Registers in use
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Architecture 37
r8
r9
r10
r11
r12
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
spsr
FIQ EXCEPTION
r8
r9
r10
r11
r12
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
spsr
Return address calculated from User mode
PC value and stored in FIQ mode LR
User mode CPSR copied to FIQ mode SPSR
38. INSTRUCTION SET
• ARM instruction set
– All instructions are 32-bit
– Most instructions can be executed conditionally
• Thumb instruction set
– 16-bit instruction set
No condition execution (except for branches)
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Architecture 38
– 16-bit instruction set
– No condition execution (except for branches)
– Optimized for code density from C code (~65% of ARM code size)
• Thumb-2 technology
– Extension to Thumb instruction set
– Mix of 16-bit and 32-bit instructions
– Condition execution via IT instruction
– Higher performance than Thumb and smaller than ARM
39. AGENDA
Introduction to ARM and the Architecture
Processor Families
Programmer’s Model
AAETC2v00
Architecture 39
Programmer’s Model
• Exceptions and Interrupts
41. ENTRY/EXIT SEQUENCE
Save processor status
Copies CPSR into SPSR_<mode>
Stores the return address in
LR_<mode>
Change processor status for exception
Mode field bits
ARM or Thumb (T2) state
Interrupt disable bits (if appropriate)
Save Regs (r1~r12) in stacks
(if necessary)
Exception handling code
Restore Regs from stacks
Applicationcode
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Architecture 41
Interrupt disable bits (if appropriate)
Sets PC to vector address
Restore CPSR from SPSR_<mode>
Restore PC from LR_<mode>
Restore Regs from stacks
(if necessary)>
Automatic processor actions Handler code
Applicationcode
42. ENTRY/EXIT INSTRUCTIONS
There are three ways of doing this…
1. Use a data processing instruction
To return from an exception,
you must…
1. Restore CPSR from SPSR
2. Restore PC from LR
This must be done atomically
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Architecture 42
1. Use a data processing instruction
MOVS PC, LR
SUBS PC, LR, #4
2. Use an LDM instruction
LDMFD sp! {pc}^
3. Use a dedicated exception return instruction
SRSFD sp!, #mode ; Save SPSR and LR to stack of specified
mode
RFEFD sp! ; Restore PC and CPSR from current mode
stack
^
43. LINK REGISTER ADJUSTMENTS
• On taking an exception …
… the link register (LR_<mode>) is automatically populated with the return
address
• Before returning …
… the link register must be adjusted, depending on the exception type
Exception Adjustment Instruction returned to
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Architecture 43
Exception Adjustment Instruction returned to
SVC 0 Next instruction
Undef 0 Next instruction
Prefetch Abort -4 Aborting instruction
Data Abort -8 Aborting instruction if precise
FIQ -4 Next instruction
IRQ -4 Next instruction
Note that there is no defined method of returning from a reset exception!
44. VECTOR TABLE
• Location of vector table
– Default to 0x00000000
– Can be relocated to 0xffff0000 in HIVECS mode
• Configurable via V bit of CP15 System Control Register
• Determined by VINITHI signal at reset
Vectors
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Architecture 44
• Content of vector table for Cortex-A/R processors
– A branch instruction
• Easy to use if handlers are within range
– LDR pc, […]
• More dynamic vector table
• Range is unlimited within address space
Vectors
LDR PC, Reset_Addr
LDR PC, Undefined_Addr
LDR PC, SVC_Addr
LDR PC, Prefetch_Addr
LDR PC, Abort_Addr
NOP ; Reserved vector
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
Reset_Addr DCD Reset_Handler
Undefined_Addr DCD Undefined_Handler
SVC_Addr DCD SVC_Handler
Prefetch_Addr DCD Prefetch_Handler
Abort_Addr DCD Abort_Handler
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
45. INTERRUPTS AND INTERRUPT
CONTROLLERS
• Most systems use an interrupt controller
ARM926EJ-SInterrupt
sources nFIQ
Interrupt
Controller
nIRQ
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Architecture 45
Most systems use an interrupt controller
– Prioritization and pre-emption
– Automatic vectoring in most cases
– Generally used for IRQ only
• IRQ/FIQ and their difference
– R8-R12 are banked in FIQ
– FIQ has higher priority than IRQ
– IRQ is disabled by processor when entering all exceptions.
FIQ is disabled by processor only when entering Reset/FIQ exception
46. SIMPLE EXCEPTION HANDLING
Save context (on stack)
Identify Interrupt resource
IRQ automatically disabled
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Architecture 46
Assembler handler
Applicationcode
Call C handler
Clear Interrupt resource
Restore context and return
C handler
IRQ automatically re-enabled
47. RE-ENABLING INTERRUPTS
• There are two ways to enable/disable interrupts
Modify CPSR Use CPS instruction
MSR r0, CPSR CPSID i
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Architecture 47
MSR r0, CPSR
BIC r0, #I_bit
MRS CPSR_c, r0
CPSID i
Works on all architectures
Uses read-modify-write so may need to be careful
Works on ARMv6 and later
Atomic operation
Can also change mode
48. RE-ENABLING INTERRUPTS
• Once IRQ is re-enabled, IRQ handlers must be re-entrant
• Problem
A fresh interrupt could occur at any time
This would cause the processor to store the return address of the new interrupt in LR_IRQ
Unless the programmer is careful, this will over-write the original return address
This will cause a program failure
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Architecture 48
This will cause a program failure
• Solution
The interrupt handler must store LR and SPSR (usually on the stack)
To prevent over-write of LR, the handler must change to another privileged mode
This must be done before re-enabling interrupts
Before exist, the handler must restore LR and SPSR
Note that a DSB instruction may be required before re-enabling
interrupts to ensure that the interrupt condition is cleared
49. RE-ENTRANT EXCEPTION HANDLING
Save LR, SPSR (on SVC stack)
Switch to SVC mode
Save {r0-r3, r12} to stack
Identify interrupt source
IRQ automatically disabled
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Architecture 49
Assembler handler
Applicationcode
Identify interrupt source
Enable IRQ
C handler
IRQ automatically re-enabled
Call C handler
Disable IRQ
Restore {r0-r3,r12} from stack
Return from SVC stack
50. SVC EXCEPTION
• SVC instruction (previously called SWI)
– Thumb SVC instruction, containing 8-bit SVC number
– SVC 0x12
– ARM SVC instruction, containing 24-bit SVC number
– SVC 0x123456
15 8 7 0
Op Code SWI number
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Architecture 50
– SVC 0x123456
• What SVC is used for?
– Implementing system call to enable user mode application calling
privilege
– Semihosting (discuss later)
2831 2427 0
Cond Op Code SWI number
23
52. ABORT EXCEPTIONS
• Aborts are caused by
– Bus error (external fault)
– Permission violation (internal fault)
– Virtual address translation failure (internal fault)
• There are two kinds of abort
– Data abort
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Architecture 52
– Data abort
• Caused by a memory or permission error on a data access
– Prefetch abort
• Caused by an error on an instruction fetch
• Instruction is flagged in the fetch stage
• Abort is taken if the instruction reaches the execution stage
• Aborts may be precise or imprecise
– For a precise abort, the instruction causing the abort can be identified
– For an imprecise abort, this is not the case
– Imprecise aborts are usually fatal (to the system or process)
53. ABORT EXAMPLES
• Examples of synchronous abort
– Attempt to access privileged memory in User mode
– Unaligned access in Strongly Ordered or Device memory
– Unaligned access when A bit in System Control Register is set
• Examples of Asynchronous abort
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Architecture 53
• Examples of Asynchronous abort
– Write which uses write bufffer
– Cache cast-out of dirty data
• Abort status information
– Abort status is stored in IFSR (for prefetch) or DFSR (for data)
– Abort address is stored in IFAR or DFAR
– DFAR contains an undefined value in the case of an imprecise abort
54. ABORT MODEL
• The “Abort Model” defines the value left in the base register for auto-
update addressing modes
• For example, if the following instruction causes an abort…
LDR r0, [r3], #4
…what value will be in r3 on entry to the abort handler?
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Architecture 54
• ARMv7 cores implement a “base-restored” abort model
• This ensures that the original, unchanged value is left in the base register
• Earlier cores (prior to ARM9) implement a “base-updated” abort model
• This leaves the updated value in the base register
• For these cores, the abort handler must contain code to determine and reverse any update to
the base register
55. UNDEF EXCEPTION
• There are several possible causes for an Undefined Instruction
exception
– An invalid instruction encoding
• This usually indicates a fatal condition e.g. attempting to execute data
– The targeted coprocessor is not available
• The exception handler may be capable of emulating the coprocessor function
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Architecture 55
• This is often used for soft FP emulation on systems with no FP hardware
support
– The targeted coprocessor is not enabled or is powered down
• The exception handler can enable (or power up) the coprocessor and then
return to retry the failed instruction
• This mechanism is sometimes used by Operating Systems to implement “lazy
context switching”
– A coprocessor is configured for Privileged or Secure access only
• The action will be system-dependent as it may indicate an attempt by a
malicious process to subvert system security