2. cache coherence?
In a single cpu system ,two copies of same data (one in cache
and other in main memory) may become inconsistent
Contents of cache and main memory can be altered by more
than one device
3. Techniques For Cache coherence (single CPU)
for avoiding Cache coherence
1) write through:- when you update cache you have to update in main
memory at same time(it takes lots of acces time due to overhead
2) Write Block:- block of data can updated at time including block of
main memory and cache memory
3) Instruction cache:- in this the property of cache changed means:-
till now data is store but we built in different way they can direcly
store instruction
4. Cache coherence (in multiprocessor environment)
for avoiding Cache coherence
1)Sharing of writeable data
2) Process migration
3)i/o activity
5. p1 p2
X
x
p1 p2 p1
x
x
X`
X`
x
x`
p2
x
1) Sharing of writeable data
Processors
cache
Shared memory
Before update Write through Write block
6. p1 p2
X
x
p1 p2 p1
x
x
X`
X`
x
x`
p2
x
2) Process migration
Processors
cache
Shared memory
Before update Write through Write block
7. p1 p2
x
p1 p2 p1
x
x
X`
X`
X`
x
p2
x
3) i/o activity
Processors
cache
Shared memory
Before update Write through Write block
x
x
x
i/o processor
