1. DAYASHANKAR SRINIVASAN
#27 kkr Avenue, Pallavan Salai, +91 9566057500
Perambur, Chennai-600011 TN, India. sdaya1988@gmail.com
Total Experience: 4 Years
CAREER OBJECTIVE:
To achieve a challenging position with a growth oriented company that value high performance,
professionalism and growth enhancement, where I can grow along with the organization with great responsibility.
EMPLOYMENT DETAILS:
Present Employment:
Working as R&D ENGINEER (FPGA) with Logic-fruit Technologies, Gurgaon / Bangalore from Nov15.
Previous Employment:
Worked as RESEARCH SCIENTIST in SAMEER CEM GOVT OF INDIA-Chennai from Dec12 – Nov15.
Experience Summary:
Design and Development
 3+ years’ experience in FPGA Design, RTL coding & verification.
 Worked on LTE based communication project as well as Filter based IP Implementation.
 Good experience in 6 and 7 series FPGA based designs.
 Good experience in Algorithm design and Digital logic development.
 Development of GUI Applications using LAB Windows CVI from National Instruments, under ‘C’ platform.
 Working level exposure to Embedded- C using KEIL-Compiler.
Testing and Debugging
 Hands on Experience in using equipment’s for signal analyzing, Logic Analyzer, Spectrum Analyzer,
Mixed signal oscilloscope, Signal generators, etc.
 Developed verification environment for system level testing for all possible failure & working conditions.
Technical Expertise:
Professional Training & Certification
 Embedded system Design at NIELIT (Govt of India) Chennai.
 FPGA based Design at NIELIT (Govt of India) Chennai.
Languages Known VHDL, VERILOG, C, EMBEDDED-C, MATLAB
Programming Tools Used Xilinx-ISE, KEIL micro V4, MATLAB, NI-
LABWINDOWS, LAB VIEW, Vivado
EDA Tool Used ISIM, MODEL SIM
FPGA’s Worked XILINX SPARTAN 6, VIRTEX 6, KINTEX 7
Communication Protocols, Interfaces RS 232, ETHERNET, PAL
Scripting Languages TCL

2. Projects Details:
LOGIC FRUIT TECHNOLOGIES
Project 4 : Development of Image Processing Application
Client : IRDE
Responsibilities
 Implementation of Matlab Designed Filter in RTL.
 System level testing of design on Kintex 7 based hardware.
 Analyzation of various image processing algorithm.
 Implementation of Bilateral Filter IP, in PAL based video Interface environment.
 TCL Based automation and verification of designed module.
 Board level implementation of the design and product functionality testing.
 Documentation work for the completed modules.
SAMEER CEM
Project 3 : TWT (CDMA)
Client : DRDO
Responsibilities
 RTL logic development for both Transmitter and Receiver Modules.
 Implementation of Matlab Developed Modules in RTL.
 Analyzing RF module with Spectrum Analyzer.
 GUI in ‘C’ language using NI LAB-WINDOWS CVI.
 Implementation and testing of the design on VIRTEX 6 based hardware.
 Documentation work for the completed modules.
Project 2 : OFDM (LTE)
Client : CORE, DIT
Responsibilities
 RTL logic development for protocol RS-232.
 Implementation of Matlab Developed Modules in RTL.
 Design and Development of Receiver Modules in RTL.
 GUI in ‘C’ language using NI LAB-WINDOWS CVI
 Supporting Hardware development for base band section OFDM_BASEBAND board.
 System level testing of design on Spartan 6 based hardware board level implementation of the design and
product functionality tested and completed product successfully released.
 Documentation work for the completed modules.

3. Project 1 : Development of Data Acquisition and Control System
Client : VECC, Department of Atomic Energy, KOLKATTA
Responsibilities
 Supported GUI Development in ‘C’ language NI LAB-WINDOWS CVI.
 Supported Development of Interface Modules using Embedded C
 Documentation work for the completed modules.
EDUCATIONAL QUALIFICATION
QUALIFICATION NAME OF THE INSTITUTION PERCENTAGE / CGPA PASS OUT YEAR
M.TECH in VLSI
(PART TIME)
VELTECH UNIVERSITY 8.15 2016
B.E in ECE Anand Institute of Higher Technology,
Anna University, Chennai.
7.13 2012
Diploma in ECE Murugappa Polytechnic College,
Chennai.
90.9 % 2009
Certificate Course in
Mechatronics
MATRIX Technical Training Centre,
Sholinghur.
70.0 % 2005 DEC
SSLC Railway Mixed High School,
Arakkonam.
77.6 % 2003
PERSONAL PROFILE
Date of Birth : 04.04.1988
Gender : Male
Marital Status : Single
Nationality : Indian
Languages known : Tamil, English, Hindi, Telugu
Alternate Email-ID : scientistdaya@gmail.com
Hobbies : Spiritual Travel, Adventure Activities, Voluntary Service,
Reading Books.
I hereby declare that the above mentioned and facts stated herein above are true, correct and complete to the best of
My knowledge and belief.
(Dayashankar.S)