VLSI Technology Trends

VLSI Technology Trends….
Dr Usha Mehta
usha.mehta@nirmauni.ac.in
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VLSITechnologyTrends...1/24/2019

Acknowledgement
This presentation has been summarized from various
books, papers, websites and presentations on VLSI
Design and its various topics all over the world. I
couldn’t remember where these large pull of hints and
work come from. However, I’d like to thank all
professors and scientists who created such a good
work on this emerging field. Without those efforts in
this very emerging technology, these notes and slides
can’t be finished.
NOTE: The figures, text etc included in slides are
borrowed from various books’ websites, authors’
books, websites, pages and other sources for
academic purpose only. The instructor does not claim
any originality.
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What if other things in life also followed the transistor’s
path?
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Courtesy: www.news18.com

What if other things in life also followed the
transistor’s path?
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What if other things in life also followed the
transistor’s path?
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Cost of Transistor
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Supply Chain of
Semiconductor World
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VLSI Companies in India
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The first Computer ENIAC
using Valve and Relays
• May 1944
• first ever general purpose
electronic computer
• by a team lead by J.P.Eckert and
J.W.Mauchly
• more than 18,000 valves, 100 by
10 by 3 feet, weight 30 tons.
• Faster than anything that had
been built previously;
multiplication in under 3 ms.
• Described as being “Faster than
thought”.
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The most important invention
in 20th Century
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The First Bipolar Transistor
• 1947: Point Contact Bipolar Transistor
• 1948: Junction Bipolar Transistor
• Bardeen, Brattain, Shockley
• -Bell Lab
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William Shockley and John Bardeen :
accepting their noble prizes on December 10, 1956
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Research vs. Failure
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Field Effect Transistor (1928)
concept –much earlier then implementation
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Shockley’s Patent Note book
(1945)
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History of Integrated
Circuit
• 1958: 1st Integrated Circuit
• Jack Kilby
• Texas Instruments
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Noble Prize in 2000

History of Integrated Circuit…..cont…
• 1959: 1st Planner(2D) Integrated Circuit
• Robert Noyce
• Fairchild Semiconductor
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History of MOS
• 1960: 1st MOSFET
• D Kahng and M Atalla
• Bell Lab
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Timeline of Electronic Devices
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Level of Integration:
Chip Complexity
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Digital Logic Families
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Si-Ge Silicon-Germanium for RF Circuits

IC Fabrication Flow
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Is it so…..!!!!!
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• Double the No. of transistor per chip:
~50 % Lithography – ability to print smaller features
~25% bigger chips/wafers
~25% design improvements
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Reduction in Transistor Size….
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Increase in Wafer Size
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Technology Windows
• Micron Technology
• Greater than or equal to 1
μm
• Sub-Micron (SM)
Technology
• 0.8 μm
• 0.6 μm
• 0.5 μm
• Deep Sub-Micron
Technology (DSM)
• 0.35 μm
• 0.25 μm
• 0.18 μm
• Ultra Deep Sub-Micron
Technology(UDSM)
• 0.15 μm
• 0.13 μm
• Nanometer
Technology
• 90 nm
• 65 nm
• 32 nm
• 28 nm
• 22 nm
• 14nm
• 10nm
• 7nm
• 5nm
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Why Moore’s Law sustained?
(point of view:1)
• Lowest cost
• Maximum Functions
• Smallest size
• highest speed
• Long lasting battery
• More reliable
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Why Moore’s Law sustained…..?
(point of view:2)
Transistor
Scaling
Better
Performance
Market Growth
Investment
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Reduction in Size
• Classical Scaling
• Reduction in L, W, TOX, VDD
• Second Age of Scaling (Equivalence Scaling)
• Reduction in L, W, TOX, VDD
• Channel Material
• Strained Silicon (SiGe)
• Stack Material
• High K
• Gate Material
• Metal Gate
• Structure
• Multi Gate
• FDSOI
• PDSOI
• Third Age of Scaling
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Classical Dennard Scaling
(1974)
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• Constant Voltage
Scaling
• Vdd constant
• More preferable
because of
peripherals
• Power
consumption
increases by …..
• Power density
increases by 3
• Constant Field
Scaling
• Seems ideal but Not a
feasible option
• to keep new chips
compatible with
existing chips, voltages
cannot be scaled
arbitrarily.
• Peripherals require
certain voltage levels at
inputs and outputs
• Multiple supply
voltages
• Complicated Level
shifter arrangement
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Effects of Scaling
• Short Channel Effects
• Narrow channel Effects
• Subthreshold Conduction
• Punch through
• Hot electrons/hot carriers
• Electromigration
• ESD
• Electric Overstress…..
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• In view of number of road blocks in standard
CMOS scaling, new device architectures were
adopted in second generation of scaling.
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Strained MOSFET
• Because of constant voltage scaling, the electric field is increased.
Strong vertical fields resulting from large Vgs cause the carriers to
scatter against the surface and also reduce the carrier mobility. This
effect is called mobility degradation
• The links between the silicon atoms become stretched - thereby
leading to strained silicon. Moving these silicon atoms farther apart
reduces the atomic forces that interfere with the movement of
electrons through the transistors and thus better mobility
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Limitation….
• Gate Oxide thickness can not be scaled down
beyond a limit because
• Processing difficulties in growing thin uniform oxide
layer ( nonuniform oxide growth “pinholes” causes
shorts between gate and substrate)
• Oxide breakdown
• Thickness of SiO₂ layer required in 45nm technology
is about 1.2nm (4 atom layers deep!!)
• Gate oxide is running out of atoms
• Quantum nature of channel electron dominates.
• Tunnelling/leakage current IG
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High K Material
• If Gate Oxide thickness can not be reduced, can we
increase the quality of gate oxide to give higher
capacitance at same thickness?
• High K Material for gate oxide to increase the insulator
capacitance while keeping a thicker oxide..
• to avoid tunnelling through the gate oxide
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Low K Material
( not in transistors but….)
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Metal-Polysilicon-Metal
• Earlier : Metal Gate
• Earlier at 5V supply, metal gates were used
• Then: Polysilicon Gate
• At lower voltages and scaling, polysilicon gate used
because of fabrication process ease.
• After initial doping, very high temp. annealing was
required during which metal gates would melt
• Again: Metal Gate
• When SiO2 is replaced with High-K material, it was
found that PolySi and High K Material were not
compatible, So polySi was replaced by metal.
• After 45nm (Intel) and 28nm (TSMC), again back to
metal gates
• To avoid poly-depletion at the poly oxide interface.
• At smaller scales, the need for a higher Vt has become
important again due to problems of leakage.
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HKMG MOSFET
• Intel’s announcement, January 26, 2007
• Hafnium-based high-k material
• Effective Oxide Thickness = 1nm
• Specific gate metals ( Intel’s trade secret)
• Different Metals for NMOS and PMOS
• Use of 193nm dry lithography
• From 65 nm to 45 nm Tech.
• Tr density: 2 times increase
• Tr switching power: 30% reduction
• Tr switching speed: 20% improvement
• S-D leakage power: 5 times reduction
• Gate oxide leakage: 10 times reduction
• 45nm processors (Core™2 family processors "Penryn")
running Windows* Vista*, Linux* etc.
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Silicon-on-Insulator (SoI)
• Lower parasitic capacitance due to
isolation from the bulk silicon,
• Resistance to latch up due to complete
isolation of the n- and p-well structures.
• Higher performance at equivalentVDD
• Reduced temperature dependency due to no doping.
• Better yield due to high density, better wafer utilization.
• Reduced antenna issues
• No body or well taps are needed.
• Lower leakage currents due to isolation thus higher
power efficiency.
• Inherently radiation hardened ( resistant to soft errors ),
thus reducing the need for redundancy. 47

FDSOI
• Fully Depleted
• Very thin layer of
buried oxide
• The region under the
channel is fully
depleted no neutral
region exists.
PDSOI
• Partially Depleted
• Thick layer of Buried
oxide
• Neutral regions
exists under channel
• Floating body effect
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Industry use of SoI
• IBM : "Istar" PowerPC-AS microprocessor
• AMD : 130 nm, 90 nm, 65 nm, 45 nm and 32 nm
single, dual, quad, six and eight core processor
• FreeScale: PowerPC 7455 CPU
• Intel did not use SoI in general but moved to HKMG
and Trigate with Conventional CMOS
• As for the traditional foundries, on July 2006,
TSMC claimed no customer wanted SOI
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Still this is not enough…..
• How should be ideal transistor?
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How SoI to Double Gate
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Double Gate to Tri-Gate
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Gate Architectures
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Tri-gate Transistor
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Tri-gate SoI Transistor
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FinFET vs. Tri-gate
• FinFET
• Spacer
• So dual gated side
gate
• Trigate
• Triple side gate
• Easy fabrication
• Improved
manufacturability
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FinFET
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FinFET
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All Around Gate Transistor
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Transistor Pathway
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Further Shrinking….
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• https://slideplayer.com/slide/1653483/

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• More Moore:
• continuous scaling,
• Already up to 7 or 5nm
• Beyond CMOS:
• new technologies such as graphene
• nanowires from the area of
Nanosciences and Nanotechnologies
• More than Moore:
• additional functionalities such as
micro/nanosystem, RF, analog,
biochips on more conventional logic or
memory circuits

ITRS Roadmap
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Roadmap for Century…..
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Courtesy: H. Iwai, Microelectronics. Eng. (2009), doi:10.1016/j.mee.2009.03.129

Adopt Natural Bio
System….
Just for example, brain of the mosquito make the
real time 3D flight control with image processing
equipped with many sensors such as infrared
and CO2 with extremely small brain volume and
extremely small energy consumption. The
performance of dragonfly’s brain is much higher.
Today’s performance and energy consumption of
the microprocessor are not comparable to those
of insect brains, at all. Introduction of the
algorithm of the bio system will be the ultimate
method in the roadmap.
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THANK YOU!
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