Memory

3. Read-Only
Memory
(ROM)
Electrically
Erasable
PROM
(EEPROM)
Mask
ROM
Erasable
PROM
(EPROM)
Ultraviolet
EPROM
(UV EPROM)
Programmable
ROM
(PROM)

4. Static
RAM
(SRAM)
Dynamic
RAM
(DRAM)
Asynchronous
SRAM
(ASRAM)
Synchronous
SRAM with
burst feature
(SB SRAM)
Extended
Data Out
DRAM
(EDO DRAM)
Burst
EDO DRAM
(BEDO
DRAM)
Fast Page
Mode
DRAM
(FPM DRAM)
Synchronous
DRAM
(SDRAM)
Random-
Access
Memory
(RAM)
Bits stored in a
semiconductor latch
or flip-flop
Bits stored as
charge on a
capacitor

5. 1
2
3
4
5
6
7
8
Row
address
decoder
Address bus Databus
Write
Memory array
Read
Columnaddress decoder
Address
Data
0
1
2
3
4
5
6
7

6. 7
6
5
4
3
2
1
0
0 0 0 0 1 1 1 1
1 1 1 1 1 1 1 1
1 0 0 0 1 1 0 1
0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 1
1 0 0 0 0 0 0 1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0 1 1
1
0 0 0
3
1
1 0 0 1
2
Read

7. 7
6
5
4
3
2
1
0
0 0 0 0 1 1 1 1
1 1 1 1 1 1 1 1
1 0 0 0 1 1 0 1
0 0 0 0 0 1 1 0
1 1 1 1 1 1 0 0
1 0 0 0 0 0 0 1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
1
1
1 0 1
1
0 0 1
2
0
1 1 0 1
3
write

9. 8KX8

10. 2KX8

11. 8KX8

13. 2KX8

14. 8KX8

16. MEMORY
ADDRESS DATA
WR
OE
CE
MWR
MRD
CS

18. mbits
m bits
Address
bus
m bits
2n bits
Control
bus
Data bus
RAM 2m´ 2n
Data
in/out
RAM 2
2m´ n
RAM 1
2m
´ n
Data
in/out
D
D
nbits n bits
(continued)

20. Data
bus
RAM 2M ´ 8
Address
bus
21 bits
Control
bus
20 bits
EN
EN
RAM 2
1M ´ 8
RAM 1
1M ´ 8
8 bits
8 bits
8 bits
20 bits
(continued)

23. 1. Expand the 2Kx8 (2716) EPROM to get 2Kx16
memory size, draw the block diagram.
2. Expand the 2KX8 (2716) EPROM to get 4KX8
memory size, draw the block diagram.
3. Expand the 2KX8 (2716) EPROM to get 8KX16
memory size, draw the block diagram.
4. How many 2716 memory chip are needed for each
case of the above?

24. 0
7 15 8 0
7
Address
BUS (20 bit)
Address
BUS (20 bit)
Data BUS
(16 bit)
Data
BUS
(16
bit) (D8-D15)
(D0-D7)
1MB 512KB 512KB
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
19 BIT
BHE A0

25. 8086 Byte access on even address ( low)
Address bus
A19 – A1
D15 – D8 D7 – D0
____
BHE ( HIGH )
Y
Y + 1
X + 1 X
A0 (LOW)
A0 is set to 0 to enable low bank
BHE is set to logic 1 to disable high bank
Data is transferred via D0 ( LSB ) – D7 ( MSB )

26. 8086 Byte access on odd address ( high bank)
Address bus
A19 – A1
D15 – D8 D7 – D0
____
BHE ( LOW )
Y
Y + 1
X + 1 X
A0 (HIGH)
A0 is set to 1 to disable low bank
BHE is set to logic 0 to enable high bank
Data is transferred via D8 ( LSB ) – D15 ( MSB )

27. 8086 Word access on even address (lowbank)-aligned
Address bus
A19 – A1
D15 – D8 D7 – D0
____
BHE ( LOW )
Y
Y + 1
X + 1 X
Both A0 and BHE is enabled ; data transferred from both banks at same
time
Data is transferred via D0 ( LSB ) – D15 ( MSB )
Aligned and occurs in 1 bus cycle
A0 (LOW)