hardware design verification

1. UNIT-5
HARDWARE DESIGN
VERIFICATION
BY
MOUNICA.J
14204127

2. Introduction to H/W acceleration & emulation.
Emulation architecture overview.
 Hardware-Accelerated Verification Systems
--->FPGA-Based Systems
--->Processor-Based Systems
 Emulator Architecture Overview
--->Small-Scale Emulation and Logic Prototyping with FPGA
--->Large-Scale Emulation with FPGA Arrays
(i) FPGA Arrays with Direct Connection Pattern
(ii) FPGA Arrays with Partial Crossbar
(iii) FPGA Arrays with Time-Multiplexed Connections
 Processor Arrays for Emulation

3. Design Modelling , Debugging, use models
 Tri-State Bus Modeling
 Independent Edge Clocking
 Aligned Edge Clocking
 Timing Control on Output
 Timing Control on Input
 Generating High-Speed Clocks
 Handling IP
---> Physical IP
---> Source Code IP
 Debugging
 Use Models

4. In circuit emulation, considerations of successful
emulation
 The Value of In-Circuit Emulation
1. Tests the design with “live” data in real world environment
2. Allows software testing to begin before first silicon, even before tape-out
3. Delivers products to market sooner
4. Reduces risk of shipping products with bugs requiring a product recall
5. Avoids performance reduction as design size grows compared to simulation
 Considerations for Successful Emulation
---> Creating an In-Circuit Emulation Environment
---> Debug Issues with Dynamic Targets
---> Considerations for Software Testing

5. Introduction to formal property verification FPG
methods & technologies
 Formal Property Verification Methods and Technologies
---> Formal Property Specification
 History of Temporal Specification Languages
---> Hardware Formal Verification Technologies/Engines
 The Automata-Theoretic Approach
 In Search of Greater Capacity
 Binary Decision Diagram-Based Symbolic Model Checking
 Satisfiability Problem-Based Bounded and Unbounded Model Checking
 Unbounded Model Checking Using a SAT Solver
 Symbolic Simulation
 Theorem Proving Methods
---> Modularization and Abstraction

6. S/W formal verification
 Software Formal Verification
---> Explicit Model Checking of Protocols
---> Explicit and Symbolic Model Checking of Java and C Programs
---> Bounded Model Checking of C Programs
---> Translation Validation of Software

7. Introduction to design for test , objectives of
DFT
 The Objectives of Design-For-Test for Microelectronics Products
1. Test Generation
--->Test Application
2. Diagnostics
3. Product Life-Cycle Considerations
---> Burn-In
---> Printed Circuit Board/Multi-Chip Module Test
---> Sub)System Support

8. Overview of chip level DFT techniques
 Brief Historical Commentary
 About Design-For-Test Tools
 Chip Design Elements and Element-Specific Test Methods
---> Digital Logic
---> Embedded Memories
---> Embedded Digital Cores
---> Embedded Field Programmable Gate Arrays

9. Introduction to automatic text pattern generation
• Test development for complex designs can be time-consuming, sometimes
stretching over several months of tedious work. In the past three decades,
various test development automation tools have attempted to address this
problem and eliminate bottlenecks that hinder the product’s time to market.
• ATPG efficiency is another important consideration. It is influenced by the
fault model under consideration, the type of circuit under test (full scan,
synchronous sequential, or asynchronous sequential), the level of
abstraction used to represent the circuit under test (gate, register transistor,
switch), and the required test quality.

10. Combinational ATPG
 Implication and Necessary Assignments
 ATPG Algorithms and Decision Ordering
 D-algorithm
 PODEM
 FAN
 SOCRATES
 Boolean Satisfiability-Based ATPG

11. Sequential ATPG
 Topological-Analysis-Based Approaches
 Undetectability and Redundancy
 Approaches Assuming a Known Reset State

12. ATPG & SAT
 Search in SAT
 Comparison of ATPG and Circuit SAT
 Combinational Circuit SAT
 Sequential Circuit SAT
 Sequential SAT and State Clauses

13. Applications of ATPG
 ATPG for Delay Faults and Noise Faults
 Design Applications
---> Logic Optimization
---> Logic Restructuring
 Design Verification
---> Logic Equivalence Checking.
---> Property Checking
---> Timing Verification and Analysis

14. High level ATPG
• Test generation could be significantly speeded up if a circuit model at a higher
level of abstraction is used.In this section, we discuss briefly the principles of
approaches using RTL models and STGs.
• Justification and fault propagation sequences generated in such a manner may not
be valid and therefore need to be verified by a fault simulator.
• A method of characterizing a design’s functional information using a model
extended from the traditional finite-state machine model, with the capability of
modeling both the data-path operations and the control state transitions.

15. Introduction to Analog & mixed analog circuit &
analog specifications
 Analog Circuits and Analog Specifications
i. Harmonic techniques
ii. Time-domain measurements
iii. Static measurements
iv. Noise measurements
 In practice, functional testing can include the following tests:
 parametric, which verifies the analog characteristics within a specified tolerance (for
example, voltages, currents, impedances, and load conditions);
 dynamic, which verifies the dynamic characteristics of the system under test — in
particular, a transient analysis in the time domain;
 static, which verifies the stable states of the system.

16. Testability analysis fault modelling & test
specification
• Testability analysis in analog circuits is an important task and a desirable approach
for producing testable complex systems.
• Testability information is useful to designers who must know which nodes to make
accessible for testing, and to test engineers who must plan test strategies.
• Test generators have become an important part of functional verification of digital
circuits. In the advent of the ever-increasing complexity of designs, decreasing
design cycles, and cost-constrained projects resulting in an increased burden on
verification engineers, design teams are becoming increasingly dependent on
automatic test generators.

17. Catastrophic fault modelling & simulation parametric
fault worst case tolerance analysis & test generation
• A DC test generation technique for catastrophic faults was developed in [27]. It
is formulated as an optimization problem and includes the effects of normal
parameter variations.
• The following steps are required for fault dictionary construction:
1. Generate the fault list; all possible shorts and opens in a circuit. Two fault-lis
extractors can be used: a layout-based fault list (standard inductive fault
analysis) and a schematic-based fault-list extractor.

18. 2. Compute the output sensitivities with respect to all hard faults in the fault list in
parallel, for example, using the adjoint network method. For example, the initial
value for Rfault can be defined as zero value resistance for the opens and as zero
value conductance for the shorts. The computed Rfault value (cause) is defined as
the smallest resistance value that if added to the circuit, will only deviate the output
parameter to the edge of the tolerance box.
3. From the fault-free circuit output tolerance ðout (effect) and the fault-free output
sensitivities S with respect to all hard faults in the fault list (obtained in step 2), the
following equation is used to compute the fault value Rfault (cause) for all the
defects in the fault list:
Rfault = ðout/Sout (Rfault)

19. DFT an overview: Analog test bus standard
The IEEE P1149.4 architecture that includes the following elements:
● Test Access Port (TAP) comprising a set of four dedicated test pins: test data in
(TDI), test data out (TDO), test mode select (TMS), test clock (TCLK), and one
optional test pin: test reset (TRSTn).
● Analog test access port (ATAP) comprising two dedicated pins: Analog test stimulus
(AT1) and analog test output (AT2), and two optional pins: inverse AT1 (AT1n)
and inverse AT2 (AT2n) for differential signals.
● Test bus interface circuit (TBIC).
● An analog boundary module (ABM) on each analog I/O.
● A digital boundary module (DBM) on each digital I/O.
● A standard TAP controller and its associated registers.

20. Oscillation based DFT/BIST
 Currently, oscillation-based approaches seem to be the most applicable in practical
implementations for all types of A/M-S devices.
 The commercial products have been developed and industrial implementations have
beensuccessful as well [49]. The popularity of oscillation-based DfT/BIST
techniques results from the following main characteristics:
 Adaptable for various functional modules: A/M-S, digital, and MEMS devices.
 Signal generator is not required.
 Immune to noise and technology-independent.
 Delivers very good fault coverage for parametric, hard, and functional errors.
 Easy to understand.

21. PLL, VCO & Jitter testing
 High-Speed Serial Links
• In serial data communication, jitter plays a key role in clock extraction and network timing.
• The recovery of the clock from the data signal poses more stringent requirements on the jitter
of the data signal than would exist when shipping a synchronous clock along with the data
signal.
• The latter is typically done in very short links, where the effort of using a full-fledged clock-
data-recovery receiver does not pay off in terms of silicon area and power consumption.
• Bit-error rate (BER) measurements or eye-diagram plots characterize the signal quality of
serial links.
• BER measurements are subject to statistical uncertainties because of the tradeoff between test
time and measurement accuracy.

22. Review of Jitter Measurement Testing
 Spectrum Analyzer Measurement
 Real-Time Time Interval Analyzer Measurements
 Repetitive Start/Stop Measurements
 ATE-Based Equipment
 Real-Time Digital Sampling Oscilloscope
 Dedicated Jitter Instrumentation
 BIST and DFT

23. ADC & DAC testing
 ADC Testing by Available ATE Systems
• Among frequently used mixed-signal circuits, data converters are typical mixed-signal devices
that bridge the gap between the analog and digital world. They determine the overall precision
and speed performances of the system and therefore, dedicated test techniques should not
affect their specifications.
• Linearity — INL, DNL: Integral and differential nonlinearity are the two basic building blocks
for ADC testing. They can be used to detect structural defects in a chip.
• Noise and distortion — SNR, SINAD, and THD: Noise and distortion can be measured
directly using sophisticated ATE instrumentation or calculated from the INL and DNL figures
while taking clock jitter into account.

24. Histogram based DFT/BIST
 The Elements of HBIST Method
 RF Test Practices
 Testing Transceiver
 Transceiver Loop—Back Technique
• It can be noted that the enhanced loop-back technique represents a functional BIST
solution aimed at enabling current tester platforms to test high-speed interfaces at-
speed, with increased functional test coverage.