1. An Efficient Architecture for Parallel Beamforming
J. F. Cruza, J. Camacho, J. M. Moreno, L. Medina
UMEDIA Group, Consejo Superior de Investigaciones Científicas (CSIC)
La Poveda (Arganda del Rey), Madrid, Spain
Background, motivation and objectives
There are many ultrasound imaging applications where fast acquisition is critical.
Cardiac sonography needs an accurate evaluation of the heart while it is contracting and
relaxing. Certain elastography techniques rely on high frame rates to measure the tissue
displacements when excited by the acoustic radiation force generated by a high intensity
pushing pulse. Also, 3D ultrasound imaging requires high frame rates. A common
technique to increase the frame rate is beamforming in parallel multiple A-scans on a
wide enough beam produced by a single transmitted pulse.
The main bottleneck of parallel beamforming is the signal-processing throughput,
particularly if dynamic focusing is used. Most approaches use multiple beamformers in
parallel to achieve this task. This approach is rather inefficient, using several hardware
resources and consuming more power. Custom ASICs allow reducing power, but
application flexibility is lost. Therefore, there is an interest on finding new architectures
that provide parallel beamforming with less hardware resources, consuming less power
and achieving high flexibility to adapt to different applications. This is the main
objective of this work.
Statement of contribution / methods
Current FPGA (Field Programmable Gate Array) generations have ASIC-like
resources specifically targeted to signal processing, called DSP blocks. They have
higher performance and consume less power than if they were implemented with
regular FPGA resources. By wisely using these DSP blocks, one can lead to new
parallel beamforming arrangements.
In this work we present a parallel beamforming architecture that exploits the
availability of these blocks in state-of-the-art FPGA. The work aims to get the
following main features:
- Optimal DSP block usage, exploiting both their switching frequency and the
number of them available per FPGA.
- Versatility: can be optimally adapted to different applications as a function of the
frequency range, number of channels, etc.
- Scalability: The system capacity can be always increased by adding more FPGAs or
using larger devices, so that it can be updated with technology improvements.
Results, discussion and conclusions
This work estimates the resource utilization and analyzes the architecture
performance in terms of number of simultaneous processed lines for different
applications.
Some realistic examples with commercially available devices are provided,
evaluating resource requirements and maximum operating frequency. For example, a
128-channel parallel beamformer, acquiring at 20 MSPS, can be built with just 4 low-
cost FPGAs, achieving frame rates of hundreds of images per second. The same system
with 4 mid-range FPGA could process the gold standard Synthetic Transmit Aperture in
real-time.

2. The architecture has high scalability, mainly restricted by communication
bandwidth between FPGA devices, that linearly with the number of parallel
beamformed lines.