1. SAI KIRAN YARAPOTINA
Mobile: (774)-312-3578 email: saik@pdx.edu
Seeking a challenging roles to utilize my technical and professional skill set for the advancement of the organization in addition to
gaining valuable experience.
WORK EXPERIENCE
Intel Corp – System Debug Intern
• Worked on enabling Microsoft designs in augmented reality with Intel Architecture, developed noteworthy skills in Post
Silicon Debug, Fault simulation and analysis, scripting for verification/validation.
• Debug Engineer for silicon and platform issues, worked extensively on customer designs.
• Skilled at using lab related tools for and test setup, hands on working with WinDbg, Lakemore, Power shell and Scope.
• Good working knowledge of system-boot procedures, BIOS, operating system and hardware enumeration.
• Experience with Python and shell scripting, defined scripts to automate and optimize the testing process.
• Analyzed and debug silicon issues related to voltage, power, frequency and thermal impact.
• Designed and conducted experiments for Regression, Graphics and Stress testing. Recommended new test cases with
emphasis on reproducibility and issue isolation.
• Power analysis through Power House Mountain and worked on CPU performance analysis.
• Gleaned working knowledge on Intel Architecture, PCIe architecture, debug tools and methodologies.
• Deployed tools for GFX, memory and battery life benchmarking on customer boards.
• Assisted in resolving gating issues on customer platforms, organized task force meetings and updated sightings.
• Good understanding in using Internal RTL tracing architecture (VISA tracing) for signal analysis.
TECHNICAL SKILLS
Hands-on : In-Target Probe, Windows Debugger, Platform Debug Tool, Windows Power shell, Lakemore,
Oscilloscope, Logic Analyzer, Intel Trace Hub, System Scope.
Software Languages : Python, C++, x86 Assembly, Verilog RTL programming.
Data Analysis : Windows Performance Analyzer, JMP, Battery Life Analyzer, Power House Mountain.
Operating Systems : Windows, Unix (Linux).
SUMMARY
• 1+ years’ experience in System Level debug and Design validation on customer platforms.
• Working knowledge across silicon, system and software teams to identify tools and test cases.
• Good understanding of unit-testing, HW architecture and validation methodology.
• Proficient in lab tools for system test and debug, signal integrity and bus interfacing.
• Hands-on experience in performing live debugging, test automation, triage and root cause analysis.
• Highly motivated in designing new logic for debug and validation.

2. EDUCATION
Portland State University, Portland, OR (June 2016)
M.S in Electrical and Computer Engineering (GPA 3.33/4)
GITAM University, India (May 2014)
B.Tech in Electronics and Electronics Engineering (GPA 3.8/4)
ACADEMIC PROJECTS (Master’s)
Set Associative L3 Cache simulation in Multiprocessor system
Designed shared memory multiprocessor configuration with PLRU replacement policy for a 64-bit processor. Enforced Inclusivity
property, cache coherency and MESIF protocol.
Design of Rojo Bot on Nexys 4 DDR - Xilinx Vivado
Implemented the working of a Rojo Bot on Artix-7 FPGA, automated motion detector and compass. Achieved Timing Specifications
for ALU implementing pipelining registers and clocking. KCPSM6 ISA.
Simulation of Instruction Set Architecture for PDP-8 computer - Verilog
Developed and verified the working of complete addressing modes and Instructions for PDP-8 Minicomputer, clock count,
instruction count and branch prediction.
Characterization of sequential cells and Memory Cell
Designed the schematic for 4x1 SRAM cell in Cadence Virtuoso and observed effect of input slope on transistor working,
analyzed setup and hold timings of the circuit.
Power system Load Forecasting
Matlab based Regression analysis for load forecasting using time series and artificial neural networks to determine influencing
factors on load requirements and error evaluation.
Smart room Illumination
Microcontroller based automatic power control system implementation using Passive Infrared Sensor, LDR and temperature
achieving 6.07% power reduction.
HONORS AND ACHIEVEMENTS
• Elected as Student Senator at ASPSU and currently seated on the Multicultural Affairs and Academic Affairs Committee, also
represented Portland State University at Oregon Students of Color Conference.
• Served as Vice President of Indian Student Association at Portland State University.
• Certified on completion of “Sustainability” course from Ecotech Institute, Aurora, Colorado.
• Represented college Badminton team in The International Sports and Cultural Carnival, RIVIERA at VIT and secured 1st
position at undergraduate level.
• Founding member K.N.O.W. (Campus Newsletter), drafted framework for operation.