Clocked Latched And Flip Flop Circuits

1. Gujarat Technological
University
Birla Vishvakarma Mahavidyalaya
Engg. College
Subject :-
VLSI Technology And Design
Prepared by:-
Kashyap Mandaliya (140083112008)
Rushi Savani (140083112015)
Pushkar Shelar (140083112016)
Guided by:-
Prof. Ghansyam B. Rathod 1140083112008,15,16

2. Clocked Latched And Flip Flop Circuits
Clocked SR Latch
CMOS SR Latch: NOR Gate Based
• The NOR-based SR Latch contains the basic
memory cell (back-to-back inverters) built
into two NOR gates to allow setting the state
of the latch.
– If Set goes high, M1 is turned on forcing Q’
low which, in turn, pulls Q high
• S=1  Q = 1
– If Reset goes high, M4 is turned on, Q is
pulled low, and Q’ is then pulled high
• R=1  Q’ = 1
– If both Set and Reset are low, both M1 and
M4 are off, and the latch holds its existing
state indefinitely
– If both Set and Reset go high, both Q and Q’
are pulled low, giving an indefinite state.
Therefore, R=S=1 is not allowed
• The gate-level symbol and truth table for the
NOR-based SR latch are given at left
• To estimate Set time, add time to discharge
Q’ + time to charge Q (pessimistic result)
2
Fig 2.1
Truth table 2.2 Logic ckt 2.3
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3. Clocked SR Latch: NOR Based
• Shown at left is the NOR-based SR latch with
a clock added.
– The latch is responsive to inputs S and R only
when CLK is high
– When CLK is low, the latch retains its current
state
• Timing diagram shows the level-sensitive
nature of the clocked SR latch.
– Note four times where Q changes state:
• When S goes high during positive CLK
• On leading CLK edge after changes in S & R
during CLK low time
• A positive glitch in S while CLK is high
• When R goes high during positive CLK
3
Logic ckt 3.1
Waveforms 3.2
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4. CMOS SR Latch: NAND Gate Based
• A CMOS SR latch built with two 2-input
NAND gates is shown at left
– The basic memory cell comprised of two
back-to-back CMOS inverters is seen
• The circuit responds to active low S and R
inputs
– If S goes to 0 (while R = 1), Q goes high,
pulling Q’ low and the latch enters Set state
• S=0  Q = 1 (if R = 1)
– If R goes to 0 (while S = 1), Q’ goes high,
pulling Q low and the latch is Reset
• R=0  Q’ = 1 (if S = 1)
– Hold state requires both S and R to be high
– S = R = 0 if not allowed, as it would result
in an indeterminate state
4
Fig 4.1
Logic ckt 4.2
Truth table 4.3
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5. Clocked CMOS SR Latch: AOI Implementation
• CMOS AOI implementation of clocked
NOR-based SR latch shown at left with
logic symbol circuit below
– Only 12 transistors required
– When CLK is low, two series legs in N
tree are open and two parallel transistors
in P tree are ON, thus retaining state in the
memory cell
– When CLK is high, the circuit becomes
simply a NOR-based CMOS latch which
will respond to inputs S and R
5
Fig 5.1
Logic ckt 5.2
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6. Clocked JK Latch
6
Logic ckt 6.2
Block diagram 6.1
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7. Clocked CMOS JK Latch: NAND Version
• The SR latch has a problem in that when both S
and R are high, its state becomes indeterminate
• The JK latch shown at left eliminates this
problem by using feedback from output to
input, such all states in the truth table are
allowable
– If J = K = 0, the latch will hold its present state
– If J = 1 and K = 0, the latch will set on the next
positive-going clock edge, i.e. Q = 1, Q’ = 0
– If J = 0 and K = 1, the latch will reset on the next
positive-going clock edge, i.e. Q’ = 1 and Q = 0
– If J = K = 1, the latch will toggle on the next
positive-going clock edge
• Note that in order to prevent the JK Latch above
from oscillating continuously during the clock
active time, the clock width must be kept smaller
than the switching delay time of the latch.
Otherwise, several oscillations may occur before
the clock goes low again. In practice this may be
difficult to achieve.
7
Logic ckt 7.1
Truth table 7.2 140083112008,15,16

8. Schematic of Clocked Nor based JK latch and CMOS AOI
realiaztion of the JK Latch
8
Logic ckt 8.1
Cmos ckt 8.2
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9. Master-Slave Flip-Flop
• A Flip-Flop is defined as two latches connected serially and activated with opposite
phase clocks
– First latch is the Master; Second latch is the Slave
– Eliminates transparency, i.e. a change occurring in the primary inputs is never reflected
directly to the outputs, since opposite phase clocks are used to activate the M and S latches.
• A JK master-slave flip-flop (NOR-based version) is shown below:
– The feedback paths occur from Q and Q’ slave outputs to the master inputs AOI gates
– does not exhibit any tendency to oscillate when J = K = 1 no matter how long the clock period,
since opposite clock phases activate the master and slave latches separately.
– The NOR-based version can be done with four AOI CMOS gates, requiring 28 transistors
– Can be susceptible to “ones catching”, i.e. a positive glitch in either the J or K input while the
CLK is high, which can change the state of the master latch (and the slave latch on next edge)
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10. 10
Block diagram 10.1
Logic ckt 10.2
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11. 11
Fig 11.1
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12. CMOS D-Latch and Edge Triggered Flip-FLop
CMOS D-Latch Implementation
• A D-latch is implemented, at the gate level, by
simply utilizing a NOR-based S-R latch,
connecting D to input S, and connecting D’ to
input R with an inverter.
– When CLK goes high, D is transmitted to output
Q (and D’ to Q’)
– When CLK goes low, the latch retains its
previous state
• The D latch is normally implemented with
transmission gate (TG) switches, as shown at
the left
– The input TG is activated with CLK while the
latch feedback loop TG is activated with CLK’
– Input D is accepted when CLK is high
– When CLK goes low, the input is open-circuited
and the latch is set with the prior data D
12
Logic ckt 12.1
Cmos ckt 12.2
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13. CMOS D-Latch Schematic View and Timing
• A schematic view of the D-Latch can be obtained
using simple switches in place of the TG’s
– When CLK = 1, the input switch is closed
allowing new input data into the latch
– When CLK = 0, the input switch is opened and the
feedback loop switch is closed, setting the latch
• Timing diagram:
– In order to guarantee adequate time to get correct
data at the first inverter input before the input
switch opens, the data must be valid for a given
time (Tsetup) prior to the CLK going low.
– In order to guarantee adequate time to set the latch
with correct data, the data must remain valid for a
time (Thold) after the CLK goes low.
– Violations of Tsetup and Thold can cause
metastability problems and chaotic transient
behavior.
13
Fig 13.1
Fig 13.2
Waveforms 13.3
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14. Alternate CMOS D-Latch Implementation
• An alternate (preferred) version of the CMOS
D-Latch (shown at left) is implemented with
two tri-state inverters and a normal CMOS
inverter.
• Functionally it is similar to the previous chart
D-Latch
– When CLK is high, the first tri-state inverter
sends the inverted input through to the second
inverter, while the second tri-state is in its high
Z state.
• Output Q is following input D
– When CLK is low, the first tri-state goes into
its high Z state, while the second tri-state
inverter closes the feedback loop, holding the
data Q and Q’ in the latch.
Cmos diagram 14.1
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15. CMOS D Flip-Flop: Falling Edge-Triggered
• Shown below is a D Flip-Flop, constructed by cascading two D-Latch circuits from the
previous chart
– Master latch is positive level sensitive (receives data when CLK is high)
– Slave latch is negative level sensitive (receives data Qm when CLK is low)
• The circuit is negative-edge triggered
– The master latch receives input D until the CLK falls from high to low, at which point it sets
that data in the master latch and sends it through to the output Qs
15
Cmos ckt 15.1
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16. Thank You 
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