1. CTU: EE443-Communication Systems I: Phase-Locked Loop 1
Colorado Technical University
EE 443- Communication Systems I
Phase-Locked Loop Research Paper
September 2010
Loren Schwappach & Crystal Brandy
ABSTRACT: This lab report was completed as a course requirement to obtain full course credit in EE443,
Communications 1 at Colorado Technical University. This report examines the components of phase-locked loop system
and its practical application in FM signal demodulation.
If you have any questions or concerns in regards to this laboratory assignment, this laboratory report, the
process used in designing the indicated circuitry, or the final conclusions and recommendations derived, please send an
email to LSchwappach@yahoo.com.
A. Modeling a PLL
I. INTRODUCTION A simple block diagram outlining the components of
a simple PLL system as used in FM demodulation is shown
This paper provides a simple outline of the phase- by Figure 1 below. The PLL frequency multiplier (Phase
locked loop process and its use and application in Detector) shown in the block diagram in Figure 1 takes in a
communication systems. Understanding of the complicated provided message input and multiplies it with an error
phase-locked loop process can be simplified through the voltage produced by a VCO. The Phase Detector outputs a
simulation and modeling of a phase-locked loop system in a voltage proportional to the phase difference between two
simulation program such as MATLAB. The process of inputs in the form of equation (5) below. This output is
demodulating a frequency modulated (FM) signal is a perfect then fed into a loop filter which is a high order low pass
model for simulating this concept and thus was chosen as the filter. The loop filter removes the unwanted high frequency
focus of this research paper. Finally, this research paper components reducing the output into the form of equation
provides a short summary of the properties inherent in a PLL (6). This loop filter output then feeds into a loop amplifier
system as well as applications of the PLL. which aids in restoring the signal into a desired amplitude.
If the carrier produced by the voltage controlled oscillator is
the same in frequency and phase as the modulated signal
II. PHASE-LOCKED LOOP then the output of the loop amplifier is the final
demodulated signal output multiplied by some factor.
A Phase-Locked Loop (PLL) is a negative feedback However, if the VCO carrier (control frequency) is not the
control system. The operation of a PLL system is closely same in frequency or phase as the modulated signal an
related to frequency demodulation. In a PLL frequency corrective error signal will attempt to drive the VCO carrier
demodulation scheme the voltage controlled oscillator’s into alignment by driving the VCO carrier either up or down
control frequency is automatically adjusted to match a in phase.
provided input signal in frequency and phase. The PLL is also
commonly used for carrier synchronization, clocking, This may seem a complicated process but can be
buffering, jitter reduction, and advanced signal processing. simplified if viewing the phase correction in a linear
manner. If equation (7) below is viewed as a x-y graph with
The phase-locked loop system consists of three the y-axis representing the VCO frequency and the x-axis
major components, a Voltage-controlled oscillator (VCO) representing an input error signal. If the input error signal
which performs frequency modulation on its internally is positive it will increase the slope of the VCO frequency
generated carrier signal, a phase detector which multiplies an deviation. If the input error signal is negative in value it will
incoming FM wave by the output of the VCO, and finally a decrease the slope of the VCO frequency deviation. This
loop filter which removes the high-frequency components change in slope will push the frequency into alignment until
contained in the multiplier’s output signal. A loop amplifier the error signal is null representing a phase-locked loop.
further aids in ensuring the demodulated output is at a
desired gain.

2. CTU: EE443-Communication Systems I: Phase-Locked Loop 2
fc t t t
t t
t t
Figure 1: Block Diagram of a PLL System used in FM The VCO produces an output whose frequency
demodulation. deviation depends directly upon the input error voltage just
like the equation for the production of an FM signal. So the
VCO can be modeled exactly the same. Figure 3 shows an
The error signal produced by the phase detector is example of how a VCO is commonly used. VCOs can be
proportional to a phase error between the VCO and a implemented in numerous ways. Some of the common
modulated signal. The error signal represents whether the methods of VCO implementation include: Crystal Oscillators
VCO correction will increase or decrease the VCO control and RLC oscillators, although they are just the beginning. The
frequency as illustrated in equation (7). time-domain equation for most common VCOs is:
Figure 2: Phase Detector represented as a multiplier.
Simple equations used for representing the inputs of
the phase detector in a FM demodulating PLL system:
s t cos fc t t
Figure 3: Commonly used VCO configuration
Comprehending the operations of a PLL system can
The output of the phase detector contains a high
be a very complex, high level mathematical nightmare when
frequency component and a low frequency component, this
viewed as a non-linear system (out of phase). However,
is due to simple triginometry.
when viewed as a linear system (In-Phase lock) the
mathematics become easy and thus the understanding of
how the PLL ensures FM demodulation and how phase lock

3. CTU: EE443-Communication Systems I: Phase-Locked Loop 3
occurs. Thus said, Figure 4 below shows the non-linear
model of a PLL assuming that the PLL is not in phase lock.
Furthermore, let us assume our VCO quiescent
(unmoved) frequency is at 10e3 Hertz. The transmission
bandwidth (BT) is not allowed to exceed 3e3 Hertz.
Figure 4: Non-Linear Mathematical Model of PLL
D. Design Considerations
Figure 5 below explains the linearized model
showing the production of the demodulated signal once the Now to fully simulate the demodulation process, we
VCO and modulated signal are in syncronization lock. need to evaluate some setup options for our VCO and Loop
filter using our design constraints above and the equations
below.
Figure 5: Linearized Mathematical Model of Locked PLL
Using these equations the following values were
B. Properties of PLL obtained for our initial design in Simulink.
Carrier frequency (fc) = 10e3 (Hz);
Some of the commonly referred to properties of a
PLL are: Step Response, or the PLL ability to phase / BT < 3e3 (Hz) so kf < 132 (Hz/V) {using max values};
frequency step onto its input (the quicker the better). Thus..
Setting Time; the amount of time needed to lock-on to a Let kf = 1e2 (Hz/V) then Beta = approx 5.5 (wideband)
signal after receiving an input (the smaller the better).
Phase Jitter; a short-term frequency instability that causes Let the LP filter cutoff at approx 1e4 (Hz) (carrier)
small, rapid movements in phase, often referred to as phase th
& use a 10 order Butterworth LP filter.
noise. The last item is one of the major strengths of PLL
systems in imaging and tracking communication systems.
E. Testing Phase
C. Simulating & Testing Now that all of the main design considerations are
taken into account we can build the system in Simulink as
Now that we have discussed some of the properties demonstrated by Figure 6a. If the design works we will then
of PLL systems and how a PLL system can be used in PM test the system using the following criteria:
demodulation, we can take all of this information about a
PLL system and use it to test a simple PLL in a FM  Test 1: Initial design
demodulation scheme created for this paper using MATLAB  Test 2: kf << 1e2
Simulink software. Suppose we are given a composite  Test 3: kf >> 1e2
sinusoidal wave as illustrated by equations (11) and (12).  Test 4: LP Filter cutoff is < 1e4 (Hz)
 Test 5: LP Filter cutoff is > 1e4 (Hz)

st
Test 6: 1 Order Butterworth LP Filter

4. CTU: EE443-Communication Systems I: Phase-Locked Loop 4
1) Initial Design
The initial design used in constructing the FM
modulator and demodulator is below. The FM modulator
portion was constructed during a previous lab in EE443
communications 1 at Colorado Technical University and
verified as a valid FM modulation scheme.
Figure 6d: Frequency components (frequency spectrum) of
the PLL demodulated signal. Notice the two major
components (above 0dBm) are the original message
frequency components.
Figure 6a: Initial Design of FM Modulation and FM
Demodulation using a PLL system.
2) Initial Design Observations
 It worked! The FM signal was successfully
demodulated using the negative phase-locked loop
feedback to lock the VCO to the modulated signal.
 The kf value of 1e2 (Hz/V) provided enough
sensitivity to accurately reproduce the message,
ensuring a quick phase lock as observed by equation
(12) while keeping the BT < 3e3 (Hz).
Figure 6b: Message signal prior to FM modulation.

th
The 10 order Butterworth low pass Loop Filter
produced a clean output signal by removing the high
frequency component garbage produced by the
phase detector (multiplier).
3) Test 2, kf << 1e2 (smaller bandwidth)
By decreasing the value of kf (VCO frequency
Figure 6c: Message signal successfully recovered using PLL sensitivity or input sensitivity) we should decrease the ability
system. of the PLL system to handle larger changes in deviation
between the VCO and the modulated signal. This should
appear as an averaging of our message signal. The results are
shown by Figure 7a.

5. CTU: EE443-Communication Systems I: Phase-Locked Loop 5
5) Test 3, kf >> 1e2 (larger bandwidth)
By increasing the value of kf we increase the capability of our
PLL VCO in tracking the phase deviations of the modulated
signal. This should increase our chances of message recovery.
However, by increasing kf we also approach exceeding our
message bandwidth and could end up pushing the PLL
outside of the frequency spectrum window (past 0Hz) as
shown by equation (14). The results of this test are shown by
Figure 7a: Time domain result of our demodulated wave figures 8a and 8b.
recovered when the PLL VCO sensitivity kf value is too low.
Notice the output signal appears almost averaged, and
notice the time it takes for our VCO to look onto the
incoming signal.
Figure 8a: By pushing kf too high our recovered signal looks
like noise in the time domain.
Figure 7b: Frequency spectrum results of setting the PLL
VCO kf value too low. Notice the drastic attenuation of our
second message component (180 Hertz).
4) Test 2, kf << 1e2 (smaller bandwidth) Figure 8b: Results of a high kf in the frequency domain.
Observations
 It failed! The FM signal was not successfully 6) Test 3, kf >> 1e2 (larger bandwidth) observations
demodulated due to the PLL VCO inability to track
the dynamically changing input.  It failed! The FM signal was not successfully
demodulated.
 The kf value of 1e1 (Hz/V) (B < .1), was not sensitive
enough to accurately reproduce the message signal  The kf value of 1e3 (Hz/V) (B > 50), was sensitive
in the time domain. Furthermore, the second enough to accurately reproduce the message
message component (180 Hz) displayed major signal in the time domain. However, the increased
attenuation compared to the first message value of kf pushed the transmission bandwidth way
component (36 Hz). above the carrier frequency and exceeding our
bandwidth requirement, ensuring a complete loss
 The Loop Filter produced a clean output signal and of information required for phase locking onto the
removed the unwanted high frequency components modulated signal.
produced by the phase detector (multiplier).
 Also, The Loop Filter would need to be adjusted (If
the BT didn’t exceed the carrier, which it did) to

6. CTU: EE443-Communication Systems I: Phase-Locked Loop 6
account for the increased frequency components  The Loop Filter failed! The LP cutoff frequency of 1
now present by the multiplier (Phase detector). kHz was to low and removed several of the pieces
(starting at the carrier) needed to accurately
represent the message.
7) Test 4, LP Filter cutoff is < 1e4 (Hz)
9) Test 5, LP Filter cutoff is > 1e4 (Hz)
In this phase the effects of a lower LP filter corner
frequency are verified on our PLL system. By lowering the By increasing our LP filter corner frequency we increase the
Loop Filters corner frequency we could cutoff several of the amount of unwanted frequency components entered into
components representing our message signal within our FM the system as a result of the Phase Detector (equation 5).
modulated wave. Removing these components could have The results of this are illustrated by Figures 10a and 10b.
drastic effects on signal recovery. The results of this filter
change are reflected by Figures 9a and 9b below.
Figure 10a: Output signal of LP Filter cutoff at 1.5e4 (HZ).
Figure 9a: Output Signal of a LP Filter with reduced corner
frequency (1e3 Hertz).
Figure 10b: Frequency Domain output of our reduced
corner LP Filter. Notice the increased amount of
undesirable signals.
Figure 9b: Output of a LP Filter with reduced corner 10) Test 5, LP Filter cutoff is > 1e4 (Hz) observations
frequency in the frequency domain. Notice our message
signal components are gone.  It failed! The FM signal was not successfully
(cleanly) demodulated.
8) Test 4, LP Filter cutoff is < 1e4 (Hz) observations
 The kf value of 1e2 (Hz/V) provided enough
sensitivity to accurately reproduce the message
 It failed! The FM signal was not successfully while keeping the BT < 3e3 (Hz).
demodulated.
 The Loop Filter failed! The LP cutoff frequency of
 The kf value of 1e2 (Hz/V) provided enough 1.5 kHz was too high and allowed several of the
sensitivity to accurately reproduce the message unwanted high frequency components into the
while keeping the BT < 3e3 (Hz). system.

7. CTU: EE443-Communication Systems I: Phase-Locked Loop 7
F. Other Applications of PLL
11) Test 5, Using a 1st Order Butterworth LP Filter
Phase-locked loop systems are essential to thousands of
By decreasing the order of the Butterworth low pass analog and digital communication devices. Among the
filter we decrease the attenuation of unwanted high
thousands are some of the following broad and commonly
frequencies present as a result of the Phase Detector. This
should show the same results as test 5, however this may used applications which include:
be even more drastic due to the poorer attenuation. The
results are shown by Figures 12a and 12b.
 Frequency Synthesizers
 Jitter reducers
 Clock Generation-
 Zero Delay Buffers
 Spread Spectrum Frequency Synthesizers
 Demodulators (QPSK, QAM, FM, FSK, SSB)
Figure 11a: Time Domain output signal of 1st order
Butterworth.
Figure 1b: Frequency Domain output of a first order
Butterworth.
12) Test 5, Using a 1st Order Butterworth LP Filter
observations
 It failed! The FM signal was not successfully
(cleanly) demodulated.
 The kf value of 1e2 (Hz/V) provided enough
sensitivity to accurately reproduce the message
while keeping the BT < 3e3 (Hz).
 The Loop Filter failed! The first order Butterworth
filter allowed several of the unwanted high
frequency components into the system.

8. CTU: EE443-Communication Systems I: Phase-Locked Loop 8
III. CONCLUSION IV. REFERENCES
nd
A Phase-Locked Loop (PLL) system is a negative Haykin, S., “Analog and Digital Communications 2
feedback control system whose operation is closely related to Edition” John Wiley & Sons, Haboken, NJ, 007.
frequency modulation (FM) and is commonly used for carrier
synchronization and indirect frequency demodulation. A PLL Truxal, J. G., Automatic Feedback Control System
system consists of three major components which are a Synthesis, McGraw-Hill, New York, 1955.
Voltage-controlled oscillator (VCO), phase detector (PD), and
loop filter. Gardner, F. M., Phase Lock Techniques, Wiley, New
York, Second Edition, 1967.
The phase-locked loop will automatically adjust its
frequency and phase based on an input error voltage and
attempt to lock onto a reference signal based upon the error.
This makes the PLL a commonly used system for carrier
synchronization, indirect frequency demodulation, clocking,
buffering, and jitter removal in digital and analog systems.

9. CTU: EE443-Communication Systems I: Phase-Locked Loop 9
Figure 7a: Initial Design of FM Modulation and FM Demodulation using a PLL system.