In this presentation, Mohamed Hafed of Introspect Technology will introduce the fundamental principles of three-phase encoding and then describe the evolutionary process involved in going from a D-PHY circuit topology to a C-PHY one. Also discussed are protocol implementation properties and guidelines for both CSI-2 and DSI-2 applications running over C-PHY links, all the while highlighting unique bandwidth, power, and encoding properties for this new SerDes standard. Practical implementation experiences that were gained when creating the world's first interoparable C-PHY systems will also be presented.

1. MIPI C-PHY℠:
Introduction
From Basic Theory to
Practical Implementation
Mohamed Hafed
Introspect Technology

2. Original Spark: Three Phase Encoding!
2
George Wiley, Qualcomm
1 Unit Interval
of Data
2.285 Bits of
Informa?on

3. Basic Concept of Three Phase Encoding
3

4. Three Voltage Levels Per Wire Ensure
Proper Differential Reception
4

5. Always-Toggle Design Allows for Simple
Clock Recovery (100% Transition Density)
5

6. Key Takeaways
6
Three-level single-ended
signaling
Non-deterministic transitions
based on self-clocked mapping
and encoding algorithm

7. Evolution from D-PHY (1 Lane, 4 Wires)
7

8. Evolution from D-PHY (1 Lane, 4 Wires)
8

9. Evolution from D-PHY (1 Lane, 4 Wires)
9

10. Evolution from D-PHY (1 Lane, 4 Wires)
10

11. Architecturally Flexible
11
Source: MIPI Alliance

12. Mapping
and Encoding
12

13. C-PHY Data Types
13
ANALOG DIGITAL
A
B
C
• 3 wires per lane
• 3-level wires (LOW, MID, HIGH)
• Every unit interval must contain
LOW, MID, and HIGH wires
• No two consecu?ve iden?cal
wire states
Symbols
(3 bits)
Integers
(16 bits)
A>B
B>C
C>A
Wire States
(3 bits)
Wire
differen?al
7-symbol to 16-
bit mapping
Wires Wire states
6
5
6 3 4 6 5 3 6
-z -y -z -x +x -z -z -y -x
0
2
2 4 1 0 0 0
0x7290

14. Wire States
14
A B C A>B B>C C>A
Wire state
name
HIGH LOW MID 1 0 0 +x
LOW HIGH MID 0 1 1 -x
MID HIGH LOW 0 1 0 +y
MID LOW HIGH 1 0 1 -y
LOW MID HIGH 0 0 1 +z
HIGH MID LOW 1 1 0 -z
ANALOG DIGITAL
(3 bits)
• A wire state is the collec?on of A, B, and C
• 6 possible wire states

15. Symbols: Now We’re Transmitting!
15
• A symbol represents a transi?on between two wire states
• 5 possible symbols
Symbol (3 bits)
Flip Rotate Polarity
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 DC DC
Rotate
0 Decr. le_er
1 Incr. le_er
Polarity
0 -
1 Toggle sign
Flip
0 -
1 Same le_er, toggle sign.
-z +x
Example:
1

16. Mapping 7 Symbols 16-bit Integers
16
• C-PHY defines a mapping between 7-symbol words and 16-bit integers
Number of 7-symbol words: Number of 16-bit integers:
65536
7-symbol words 16-bit integers
65536
12589
unmapped
words
1-to-1
mapping
{0224100} 0x7290
{3444443}
{4444444}
Sync Word (Alignment marker)
Post (End-of-Packet marker)

17. Well Defined Algorithms from MIPI Alliance
17

18. 18
“Don’t
Even Worry
About It”

19. Eco-System Is Developed for Tools
19
Three-Phase
Signals
Decoded Data

20. Anatomy of a Packet Transmission
20

21. Practical
Experiences
21

22. Tx: Both Mapping and Encoding Before
Serializer
22

23. Rx: Avoiding False Sync Detection
(Problem Statement)
23

24. Rx: Avoiding False Sync Detection
(Solution)
24
Detect SYNC with Pre-End as Marker for Start of Transmission

25. CSI-2 Long Packets in C-PHY
25

26. CSI-2 Long Packets in C-PHY
26

27. CSI-2 Long Packets in C-PHY
27

28. CSI-2 Long Packets in C-PHY
28

29. CSI-2 Long Packets in C-PHY:
The Invisible SYNC
29

30. DSI-2 Long Packets in C-PHY
30

31. DSI-2 Long Packets in C-PHY
31

32. DSI-2 Long Packets in C-PHY
32

33. DSI-2 Long Packets in C-PHY
33

34. DSI-2 Sample Protocol Analyzer Trace
34

35. DSI-2 Sample Protocol Analyzer Trace
35

36. Key Takeaways
36
Tx mapping and encoding in parallel domain
Rx false sync avoidance required pre-begin
monitoring
Packet header definition required careful
design of SYNC manipulation (both Tx and Rx)
CSI-2 & DSI-2 treat SYNC insertion differently

37. April 10, 2014: World’s First C-PHY
Interoperability!
37
Leading Image Sensor
Manufacturer Test Chip
(Tx)
2.0
Gsps
First Packet Received First Eye Diagram