G. Oliver Stone is a principal-level software engineer with 18 years of experience seeking a senior software design position. He has expertise in embedded software development, communication standards, HDL design, and implementation tools like C++, Python, Verilog, and FPGA design tools. His accomplishments include developing test scripts, diagnostic functions, applications, games, and optical module FPGAs. He has worked as a principal engineer developing FPGAs and Python test systems, and as an ASIC architect and DSP designer.

1. G. Oliver Stone
(603) 883-0086 (Home) ostone@charter.net 41 Louise Dr.
(603) 508-2419 (Cell) Hollis, NH 03049
Objective: Senior Software Design Position
Summary
A highly productive, principal-level engineer with eighteen years of experience in the communications field looking
to concentrate more fully on software design.
Expertise in the following technologies:
• Embedded software development and scripting.
• LAN and WAN communication and interconnect standards (10/100/1000Base-T, POS, ATM, T/E3, PCIe,
HyperTransport).
• HDL design. Control and data path structures. Multiple clock domains. Resource sharing. Efficient use of
DSP blocks in FPGAs. DSP techniques in FPGA design.
Expertise with the following implementation tools:
• C, C++, Python, Java, Javascript and Perl programming languages in both Windows and UNIX
environments.
• Verilog and SystemVerilog. (Working knowledge of VHDL).
• Altera, Xilinx, and Lattice tool flows and the Synplicity and ModelSim tools.
• Mentor schematic capture and Cadence layout tools.
• Lab equipment (SmartBits, Agilent and TEK oscilloscopes and logic analyzers, soldering station tools).
Accomplishment Highlights
• Created a test script in Python to bring up a module and run a number of tests while recording the
results. This allowed the module to run through its functions in a thermal chamber for nine-corner testing. The
script ran on cygwin, but had to launch a native Windows script to connect to some of the test equipment. It
allowed the hardware under test to be connected to via telnet or a COM link and it output an Excel file with the
results.
• Wrote diagnostic functions to test a quad 100Base-TX MAC/PHY and other parts of a router services
card. These functions were written in C and used in a test suite for Quality Assurance and debugging.
• Wrote stand-alone applications that were included in the release of a foreign language teaching
software under Microsoft Windows using the C++ MFC libraries. These applications allowed the user to
practice using the foreign language in an interactive and entertaining way.
• Performed half of all design and coding of Game-Maker. Game-Maker was a WYSIWYG CAD
product for creating tile-based arcade-style games for (486 era) PCs. It enabled users to create original games
without any coding. Built using C and C++, Game-Maker incorporated features such as animation, music, sound
effects, and full-screen scrolling. Set up and manned the company’s booth at the Consumer Electronics Show in
Chicago.
• Designing an active web email client application using Meteor with a Mongo backend database on
github. Coding is done in Javascript.
• Created a simple interactive Android game using Java under eclipse.
• Specified, designed, wrote, compiled and tested control-path FPGAs using Verilog for several 40-
100Gbps optical modules using the Xilinx Spartan6 family. These FPGAs interface to the card's processor and
ASICs and also contain control loops to keep the optics at their optimal operating points. One of these control
loops comprised the injection of a dither tone onto a bias voltage through an off-chip DAC, retrieval of the
output signal from an ADC, signal processing to extract the effect of the dither tone using DSP blocks, and then
adjustment of the bias voltage according to the result. Implementing the optics control loops digitally in the
FPGA saved valuable board space, allowing a size reduction of the module.
• Wrote HDL as part of a three person team for a 108,000-register FPGA with 7Mbits of memory,
targeted to an Altera Stratix II 180 part. This design offloads up to two companion packet processors and
enables generic classification, shaping, and replication of traffic at 10Gbps bi-directionally. My individual

2. accomplishments included interfacing to Altera’s SPI4.2 core, designing an interface to an external TCAM, and
creating a weighted round robin algorithm to choose between multicast and unicast traffic. Created design
constraints and performed the design compilation. Worked closely with the design verification team and the
board design teams to smooth out issues with their tests. This design allows significant performance
improvements over designs based on the packet processor alone.
• Implemented a multiple-channel modulator which allowed different modulation modes and symbol
rates in an FPGA. Coded a module for BPSK, QPSK, 8PSK , and QAM encoding, one for an optimized root-
raised cosine FIR filter, and glue logic to support between 1 and 48 channels at various bandwidths. Optimized
the FIR filter design to take advantage of reuse among channels and zeros in the interpolated input stream.
• Architected and implemented a board design for an I/O base card for a LAN/WAN security router.
Custom base card used either off-the-shelf PMC daughter cards for low-bandwidth IO or custom
HyperTransport based cards for high-bandwidth I/O. Designed and coded an FPGA for data path processing
and backplane interfacing with a custom SERDES protocol. Schematic design included a Broadcom
communications processor for packet processing and control, PCI bridge to Fast Ethernet MACs for interfacing
two redundant Switch/Services Cards, dual DDR DIMM interfaces, I²C peripherals, and HT and PCI interfaces
for daughter cards. Also responsible for the FPGA implementation of the backplane protocol and system
control.
Experience
July 2009 to July 2014. Oclaro, Inc., Acton, MA.
Principal Hardware Engineer
• Oclaro's only FPGA designer in New England. Primarily created FPGAs as optics control systems.
• Created SystemVerilog test bench suite to verify designs.
• Wrote Python system to test hardware and gather real-time operational data over varying environmental
conditions.
February 2009 to July 2009. Innovative Communications Engineering, LLC. (ICE) North Chelmsford, MA.
Principal Hardware Engineer
• ASIC architect for satellite communications system.
• DSP designer for FPGA-based low-cost modulator.
July 1998 to January 2009. Nortel Networks Billerica, MA.
Hardware Engineer, JCI 4
• HDL designer for FPGA/ASIC packet manager.
• Designer of an I/O base card for a LAN/WAN security router.
◦ Wrote diagnostic routines to test several elements on this card.
◦ Created Microsoft Access database to manage prototype modules and keep track of their current
rework level and their issues or diagnostic test failures.
• Designer of a management card for a multi-service switch, taken from an inherited proof-of-concept design.
• Member of a design team responsible for a 108,000 register FPGA (appox 1.5M gates).
January 1997 to July 1998. Cabletron Systems’ Digital Network Products Group (via the acquisition of Digital
Equipment’s High-Performance Network division by Cabletron). Littleton, MA.
Hardware Engineer
• FPGA and hardware designer of an ATM switch line card.
Fall 1994 to December 1996. Northwestern University Evanston, IL.
• Created Master’s thesis that analyzed available ASIC technologies.
Summer 1994. Transparent Language Hollis, NH.
• Software engineer developing foreign-language interactive software in C++.
Winter to Spring 1994. Yale University New Haven, CT.
• As an undergraduate, added a new algorithm using C++ to existing circuit timing analyzer software.
1990-1993. Recreational Software Designs Amherst, NH.
Vice-President and Co-Founder
• Software engineer creating computer game development systems.

3. CAE Tool Experience
CAE Tools:
• Eclipse, Meteor, Altera’s Quartus II, Altera Qsys, Xilinx ISE and Vivado; Xilinx System Generator for
DSP, Xilinx XPS (EDK tool), Lattice Diamond; Synopsys' Synplify; Mentor's Modelsim and Questa;
Cadence’s Allegro, Mentor's DX Designer (ViewDraw). Emacs. Eclipse programming environment.
Test Equipment:
• HP (Agilent) and Tektronix scopes and logic analyzers; SmartBits and Adtech traffic generators/analyzers;
DVMs; optical power meters, modulation analyzers, and spectrum analyzers.
Education
Northwestern University, M.S. Electrical Engineering, 1996
Yale University, B.S. Electrical Engineering, 1994
The Derryfield School, Manchester, New Hampshire, Graduated 1990
Research Science Institute, Washington D.C., Summer 1989
Honors and Awards
Walter P. Murphy Fellowship Recipient (Northwestern)
National Merit Scholarship Finalist
Dartmouth Book Award
Rensselaer Polytechnic Institute Medal for Mathematics and Science
1990 Derryfield Scholar Athlete Award; Math Award; Science Award
Selected as a Research Science Institute student (about 80 students selected annually world wide)