The Serial Peripheral Interface or SPI bus is a synchronous serial data link, a de facto standard, named by Motorola, that operates in full duplex mode. It is used for short distance, single master communication, for example in embedded systems, sensors, and SD cards.
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The I2C Bus
• What is the I2C Bus and what is it used for?
• Bus characteristics
• I2C Bus Protocol
• Data Format
• Typical I2C devices
• Example device
• Sample pseudo code
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What is I2C
• The name stands for “Inter - Integrated Circuit Bus”
• A Small Area Network connecting ICs and other electronic
systems
• Originally intended for operation on one
single board / PCB
– Synchronous Serial Signal
– Two wires carry information between
a number of devices
– One wire use for the data
– One wire used for the clock
• Today, a variety of devices are available with I2C Interfaces
– Microcontroller, EEPROM, Real-Timer, interface chips, LCD driver, A/D
converter
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What is I2C used for?
• Data transfer between ICs and systems at relatively
low rates
– “Classic” I2C is rated to 100K bits/second
– “Fast Mode” devices support up to 400K bits/second
– A “High Speed Mode” is defined for operation up to 3.4M
bits/second
• Reduces Board Space and Cost By:
– Allowing use of ICs with fewer pins and smaller packages
– Greatly reducing interconnect complexity
– Allowing digitally controlled components to be located
close to their point of use
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I2C Bus Characteristics
• Includes electrical and timing specifications,
and an associated bus protocol
• Two wire serial data & control bus implemented with the
serial data (SDA) and clock (SCL) lines
– For reliable operation, a third line is required:
Common ground
• Unique start and stop condition
• Slave selection protocol uses a 7-Bit slave address
– The bus specification allows an extension to 10 bits
• Bi-directional data transfer
• Acknowledgement after each transferred byte
• No fixed length of transfer
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I2C Bus Characteristics (cont’d)
• True multi-master capability
– Clock synchronization
– Arbitration procedure
• Transmission speeds up to 100Khz
(classic I2C)
• Max. line capacitance of 400pF,
approximately 4 meters (12 feet)
• Allows series resistor for IC protection
• Compatible with different IC technologies
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I2C Bus Definitions
• Master:
– Initiates a transfer by generating
start and stop conditions
– Generates the clock
– Transmits the slave address
– Determines data transfer direction
• Slave:
– Responds only when addressed
– Timing is controlled by the clock line
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I2C Hardware Details
• Devices connected to the bus must have an open drain or
open collector output for serial clock and data signal
• The device must also be able to sense the logic level on
these pins
• All devices have a common ground reference
• The serial clock and data lines are connected to Vdd(typically
+5V) through pull up resistors
• At any given moment the I2C bus is:
– Quiescent (Idle), or
– in Master transmit mode or
– in Master receive mode.
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I2C Electrical Aspects
• I2C devices are wire ANDed together.
• If any single node writes a zero, the entire line is zero
11. I2C Bus Configuration
• 2-wire serial bus – Serial data (SDA) and Serial clock (SCL)
• Half-duplex, synchronous, multi-master bus
• No chip select or arbitration logic required
• Lines pulled high via resistors, pulled down via open-drain drivers
(wired-AND)
12. I2C Protocol
1. Master sends start condition (S) and controls the clock signal
2. Master sends a unique 7-bit slave device address
3. Master sends read/write bit (R/W) – 0 - slave receive, 1 - slave transmit
4. Receiver sends acknowledge bit (ACK)
5. Transmitter (slave or master) transmits 1 byte of data
13. I2C Protocol (cont.)
6. Receiver issues an ACK bit for the byte received
7. Repeat 5 and 6 if more bytes need to be transmitted.
8.a) For write transaction (master transmitting), master issues stop
condition (P) after last byte of data.
8.b) For read transaction (master receiving), master does not acknowledge
final byte, just issues stop condition (P) to tell the slave the
transmission is done
14. I2C Signals
• Start – high-to-low transition of the SDA line while SCL line is high
• Stop – low-to-high transition of the SDA line while SCL line is high
• Ack – receiver pulls SDA low while transmitter allows it to float high
• Data – transition takes place while SCL is slow, valid while SCL is high
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Bit Transfer on the I2C Bus
• In normal data transfer, the data line only changes state
when the clock is low
SDA
SCL
Data line stable;
Data valid
Change
of data
allowed
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Start and Stop Conditions
A transition of the data line while the clock line is high is
defined as either a start or a stop condition.
Both start and stop conditions are generated by the bus
master
The bus is considered busy after a start condition, until a stop
condition occurs
Start
Condition
Stop
Condition
SCL SCL
SDASDA
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I2C Addressing
• Each node has a unique 7 (or 10) bit address
• Peripherals often have fixed and programmable
address portions
• Addresses starting with 0000 or 1111 have
special functions:-
– 0000000 Is a General Call Address
– 0000001 Is a Null (CBUS) Address
– 1111XXX Address Extension
– 1111111 Address Extension – Next Bytes are the
Actual Address
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MSB
ACK
LSB
7 – Bit Slave Address
R / Wr
First Byte in Data Transfer on the I2C Bus
R/Wr
0 – Slave written to by Master
1 – Slave read by Master
ACK – Generated by the slave whose address has been output.
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I2C Bus Connections
• Masters can be
– Transmitter only
– Transmitter and receiver
• Slaves can be
– Receiver only
– Receiver and transmitter
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Acknowledgements
• Master/slave receivers pull data line low for one clock pulse
after reception of a byte
• Master receiver leaves data line high after receipt of the last
byte requested
• Slave receiver leaves data line high on the byte following the
last byte it can accept
Acknowledgement
from receiver
Transmitter releases SDA
line during 9th clock
pulse.
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Acknowledgements
• From Slave to Master Transmitter:
– After address received correctly
– After data byte received correctly
• From Slave to Master Receiver:
– Never (Master Receiver generates ACK)
• From Master Transmitter to Slave:
– Never (Slave generates ACK)
• From Master Receiver to Slave:
– After data byte received correctly
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Negative Acknowledge
• Receiver leaves data line high for one clock
pulse after reception of a byte
Not acknowledgement
(NACK) from receiver
Transmitter releases SDA
line during 9th clock
pulse.
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Negative Acknowledge (Cont’d.)
• From Slave to Master Transmitter:
– After address not received correctly
– After data byte not received correctly
– Slave Is not connected to the bus
• From Slave to Master Receiver:
– Never (Master Receiver generates ACK)
• From Master Transmitter to Slave:
– Never (Slave generates ACK)
• From Master Receiver to Slave:
– After last data byte received correctly
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Data Transfer on the I2C Bus
• Start Condition
• Slave address + R/W
– Slave acknowledges with ACK
• All data bytes
– Each followed by ACK
• Stop Condition
ACK from Slave ACK from
Receiver
Remember : Clock is produced by Master
Start Stop
SCL
SDA
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Data Formats
Master writing to a Slave
AAA
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Data Formats Cont’d.
Master reading from a Slave :
Master is Receiver of data and Slave is Transmitter of data.
1
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Data Formats Cont’d.
Combined Format
A repeated start avoids releasing the bus and therefore
prevents another master from taking over the bus
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Multi-master I2C Systems
• Multimaster situations require two additional
features of the I2C protocol
• Arbitration:
– Arbitration is the procedure by which competing
masters decide final control of the bus
– I2C arbitration does not corrupt the data transmitted
by the prevailing master
– Arbitration is performed bit by bit until it is uniquely
resolved
– Arbitration is lost by a master when it attempts to
assert a high on the data line and fails
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Arbitration Between Two Masters
• As the data line is like a wired AND, a ZERO address bit overwrites a ONE
• The node detecting that it has been overwritten stops transmitting and
waits for the Stop Condition before it retries to arbitrate the bus
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Error Checking
• I2C defines the basic protocol and timing
– Protocol errors are typically flagged by the interface
– Timing errors may be flagged, or in some cases could
be interpreted as a different bus event
• Glitches (if not filtered out) could potentially
cause:
– Apparent extra clocks
– Incorrect data
– “Locked” bus
• Microprocessors communicating with each
other can add a checksum or equivalent
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Bus Recovery
• An I2C bus can be “locked” when:
– A Master and a Slave get out of synch
– A Stop is omitted or missed (possibly due to noise)
– Any device on the bus holds one of the lines low
improperly, for any reason
– A shorted bus line
• If SCL can be driven, the Master may send extra
clocks until SDA goes high, then send a Stop.
• If SCL is stuck low, only the device driving it can
correct the problem.
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Type of I2C Implementations
• Byte Oriented Interface
– Data is handled one byte at a a time
– Processor interprets a status byte when an event occurs
– For instance Philips 8xC554, 8xC591
• Bit Oriented Interface
– Processor is involved in every bus event when the interface is not Idle
• “Bit Banged”
– Implemented completely in software on 2 regular I/O pins of the
microcontroller
– Works for single master systems
– Not recommended for Slave devices or Multimaster systems
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Available I2C Devices
• Analog to Digital Converters (A/D, D/A): MMI functions,
battery & converters, temperature monitoring, control
systems
• Bus Controller: Telecom, consumer electronics, automotive,
Hi-Fi systems, PCs, servers
• Bus Repeater, Hub & Expander: Telecom, consumer
electronics, automotive, Hi-Fi systems, PCs, servers
• Real Time Clock (RTC)/Calendar: Telecom, EDP, consumer
electronics, clocks, automotive, Hi-Fi systems, FAX, PCs,
terminals
• DIP Switch: Telecom, automotive, servers, battery &
converters, control systems
• LCD/LED Display Drivers: Telecom, automotive instrument
driver clusters, metering systems, POS terminals, portable
items, consumer electronics
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Available I2C Devices
• General Purpose Input/Output (GPIO) Expanders and LED
Display Control: Servers, keyboard interface, expanders,
mouse track balls, remote transducers, LED drive, interrupt
output, drive relays, switch input
• Multiplexer & Switch: Telecom, automotive instrument driver
clusters, metering systems, POS terminals, portable items,
consumer electronics
• Serial RAM/ EEPROM: Scratch pad/ parameter storage
• Temperature & Voltage Monitor: Telecom, metering systems,
portable items, PC, servers
• Voltage Level Translator: Telecom, servers, PC, portable
items, consumer electronics
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End use
• Telecom: Mobile phones, Base stations,
Switching, Routers
• Data processing: Laptop, Desktop,
Workstation, Server
• Instrumentation: Portable instrumentation,
Metering systems
• Automotive: Dashboard, Infotainment
• Consumer: Audio/video systems, Consumer
electronics (DVD, TV etc.)
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Applications
• There are some specific applications for
certain types of I2C devices such as TV or radio
tuners, but in most cases a general purpose
I2C device can be used in many different
applications because of its simple
construction.
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I2C designer benefits
• Functional blocks on the block diagram
correspond with the actual ICs; designs proceed
rapidly from block diagram to final schematic
• No need to design bus interfaces because the I2C-
bus interface is already integrated on-chip
• Integrated addressing and data-transfer protocol
allow systems to be completely software-defined
• The same IC types can often be used in many
different applications
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I2C designer benefits
• Design-time improves as designers quickly become familiar
with the frequently used functional blocks represented by I2C-
bus compatible ICs
• ICs can be added to or removed from a system without
affecting any other circuits on the bus
• Fault diagnosis and debugging are simple; malfunctions can
be immediately traced
• Software development time can be reduced by assembling a
library of reusable software modules
• The simple 2-wire serial I2C-bus minimizes interconnections so
ICs have fewer pins and there are fewer PCB tracks; resulting
in smaller and less expensive PCBs
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I2C Manufacturers benefits
• The completely integrated I2C-bus protocol eliminates the
need for address decoders and other ‘glue logic’
• The multi-master capability of the I2C-bus allows rapid
testing/alignment of end-user equipment via external
connections to an assembly-line
• Increases system design flexibility by allowing simple
construction of equipment variants and easy upgrading to
keep design up-to-date
• The I2C-bus is a de facto world standard that is implemented
in over 1000 different ICs (Philips has > 400) and licensed to
more than 70 companies
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Example – EEPROM (Part 24WC32)
• 400 KHz I2C Bus Compatible*
• 1.8 to 6 Volt Read and Write
Operation
• Cascadable for up to Eight Devices
• 32-Byte Page Write Buffer
• Self-Timed Write Cycle with Auto-
Clear
• Zero Standby Current
• Commercial, Industrial and
Automotive Temperature Ranges
Write Protection– Entire
Array Protected When WP at
VIH
1,000,000 Program/Erase
Cycles
100 Year Data Retention
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Writing a Single Data Byte
After the STOP bit is receive the device internally programs
the EEPROM with the received data byte.
The programming can take up to 10ms (max.). The device
will be busy during this period and will not respond to its
slave address.
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Writing Multiple Bytes (Page Write)
The bytes are received by the device and stored internally in a buffer
before being programmed into the EEPROM.
A maximum of 32 bytes (one page = 32 bytes) may be written at one
time for the 24WC32 device.
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Reading EEPROM
Read current location
Read specified location – Note repeated start to
prevent loss of bus during read process.
46. Introduction - SPI
What is it?
Basic Serial Peripheral Interface (SPI)
Capabilities
Protocol
Pro / Cons and Competitor
Uses
Conclusion
Serial Peripheral Interface
47. What is SPI?
• Serial Bus protocol
• Fast, Easy to use, Simple
• Everyone supports it
48. SPI Basics
A communication protocol using 4 wires
Also known as a 4 wire bus
Used to communicate across small
distances
Multiple Slaves, Single Master
Synchronized
49. Capabilities of SPI
Always Full Duplex
Communicating in two directions at the same
time
Transmission need not be meaningful
Multiple Mbps transmission speed
Transfers data in 4 to 16 bit characters
Multiple slaves
Daisy-chaining possible
50. Protocol
Wires:
Master Out Slave In (MOSI)
Master In Slave Out (MISO)
System Clock (SCLK)
Slave Select 1…N
Master Set Slave Select low
Master Generates Clock
Shift registers shift in and out data
51. Advantages and drawbacks
• SPI is a very simple communication protocol.
– It does not have a specific high-level protocol which means that there is almost no
overhead.
• Data can be shifted at very high rates in full duplex mode
– This makes it very simple and efficient in a
single master single slave scenario.
• The exchange itself has no pre-defined protocol. This makes it ideal for
data-streaming applications.
• Data can be transferred at high speed, often into the range of the tens of
megaHertz.
• The flipside is that there is no acknowledgment, no flow control, and the
master may not even be aware of the slave's presence / or absence.
– You could do “some” handshaking via software
52. Systems that use SPI
The question is of course, which peripheral types exist
and which can be connected to the host processor.
Peripheral types can be subdivided into the following
categories:
– Converters (ADC and DAC)
– Memories (EEPROM and FLASH)
– Real Time Clocks (RTC)
– Sensors (temperature, pressure)
– Others (signalmixer, potentiometer, LCD controller, UART, CAN
controller, USB controller, amplifier)
53. Concept of Master and Slave
• Master
– The component
that initiates the
transfer
– The component
that controls the
transfer
• Slave
– The component
that responds to
the transfer
54. Master / Slave concept
Slave Select (Chip Select)
• Master sends out
active low chip
select signal SS1,
then slave 1
responds
• Master sends out
active low chip
select signal SS2,
then slave 2
responds
FOR SAFETY – SELECT SIGNAL IS “ACTIVE LOW” NOT “ACTIVE HIGH”
55. Master / Slave concept
Master to Slave data movement
• Master sends out
information to slave on
MOSI wire
• Slave receives
information from the
master on MOSI wire
• Information (bits) is
clocked by SCLK signal.
– 1-bit, 1 clock tick
MOSI --MASTER OUT – SLAVE IN
56. Master / Slave concept
Slave to Master data movement
• Master receives
information from slave
on MISO wire
• Slave sends
information to the
master on MISO wire
• Information (bits) is
clocked by SCLK signal.
– 1-bit, 1 clock tick
MISO --MASTER IN – SLAVE OUT
57. Wires in Detail
MOSI – Carries data out of Master to Slave
MISO – Carries data from Slave to Master
Both signals happen for every transmission
SS_BAR – Unique line to select a slave
SCLK – Master produced clock to
synchronize data transfer
58. Shifting Protocol
Master shifts out data to Slave, and shift in data from Slave
http://upload.wikimedia.org/wikipedia/commons/thumb/b/bb/SPI_8-bit_circular_transfer.svg/400px-SPI_8-bit_circular_transfer.svg.png
59. Diagram
Master and multiple independent
slaves
Master and multiple daisy-
chained slaves
Some wires have been renamed
60. Clock Phase (Advanced)
Two phases and two polarities of clock
Four modes
Master and selected slave must be in same
mode
Master must change polarity and phase to
communicate with slaves of different
numbers
62. Pros and Cons
Pros:
Fast and easy
Fast for point-to-point connections
Easily allows streaming/Constant data inflow
No addressing/Simple to implement
Everyone supports it
Cons:
SS makes multiple slaves very complicated
No acknowledgement ability
No inherent arbitration
No flow control
63. Uses
Some Serial Encoders/Decoders,
Converters, Serial LCDs, Sensors, etc.
Pre-SPI serial devices
PPC
PPC implements SPI well
The bus of choice for communicating with
small peripherals
64. Conclusion
SPI – 4 wire serial bus protocol
MOSI MISO SS SCLK wires
Full duplex
Multiple slaves, One master
Best for point-to-point streaming data
Easily Supported
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UART (Universal Asynchronous Receiver/Transmitter)
• Most UARTS are full duplex – they have separate pins and
electronic hardware for the transmitter and receiver that
allows serial output and serial input to take place
simultaneously.
• Based around shift registers and a clock signal.
• UART clock determines baud rate
• UART frames the data bits with
– a start bit to provide synchronisation to the receiver
– one or more (usually one) stop bits to signal end of data
• Most UARTs can also optionally generate parity bits on
transmission and parity checking on reception to provide
simple error detection.
• UARTs often have receive and transmit buffers(FIFO's) as well
as the serial shift registers
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UART - Transmitter
• Transmitter (Tx) - converts data from parallel
to serial format
– inserts start and stop bits
– calculates and inserts parity bit if required
– output bit rate is determined by the UART clock
Serial output
Parallel
data
UART Clock from
baud rate generator
Status information
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UART - The Receiver
– synchronises with transmitter using the falling edge of the start bit.
– samples the input data line at a clock rate that is normally a multiple of
baud rate, typically 16 times the baud rate.
– reads each bit in middle of bit period (many modern UARTs use a
majority decision of the several samples to determine the bit value)
– removes the start and stop bits, optional calculates and checks the
parity bit. Presents the received data value in parallel form.
Serial input
Status information
Parallel
data
UART Clock from
baud rate generator
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UARTs
• Usually used on simple systems
• Typically point to point communications
• Various different formats and protocols
• Normally 8-bit data format with one start and one stop bit
• Standards: E.g. RS232
– defines connector type, pin assignments, voltage levels, max bit rate,
cable length etc.
– Min. 3 pins – TxD, RxD, Ground
– Other pins for data flow control.
• Some common RS232 baud rates - 300,1200,9600,19200
• Handshaking
– None
– Hardware - RTS, CTS, etc - simple logic levels
72. The LPC23xx UARTs
• UART1 is identical to UART0/2/3, but with the
addition of a modem interface.
• 16 byte Receive and Transmit FIFOs.
• Register locations conform to ‘550 industry
standard.
• Receiver FIFO trigger points at 1, 4, 8, and 14
bytes.
• Built-in baud rate generator.
• Standard modem interface signals included 7-72
73. UART Registers
• Control registers
• Transmit
• Receive
• FIFO control
• Status
• Interrupt
• Interrupt enable
• Format control
• Baud rate control 7-73
