2. R-S-Flip-Flop-(R/S F/F)
Flip-flop is important memory device is used to
store one binary digit 0 or 1.Flip-Flop is the two
stable state circuit like bi-stable multivibrator
circuit. These circuit can stay in one stable state ,it
did not change its stable state unless one can give
an external trigger or external force(Example of
bulb)
Fig.Bistable circuit.
For example consider the bistable circuit made by
two NOT gates in series combination.It has an two
stable states that are
Y=0 and Y = 1 or
Y=1 and Y = 0 ..
• Also circuit can stable in any one of these state. It
does not change the state of it unless external
trigger was supplied
• A flip-flop is a two-state circuit that can
remain in either state indefinitely. It is also
called as bistable multivibrator.
• Without any external triger it can’t change the its
state or output state.
• Different types of flip- flops are explained below.
1)R-S flip-flop(Reset-Set Flip-Flop)
2)R-S Clocked Flip-Flop
3)J-K Flip-Flop
4)D-Latch or D- Flip- Flop
5)J-K M/S Flip- Flop J-K Master Slave Flip-Flop.
3. R-S flip-flop using NOR-gates:
R-S Flip-Flop can be constructed using NOR gate
and NAND gate.
• R-S flip-flop can be constructed by using two NOR gates.
The output of each NOR-gate is connected to one of
the inputs of the other NOR-gate. S - (Set) and R - (Reset)
inputs allows to set or reset flip-flop.
• R-S Flip-Flop Using NOR gate.
• Fig.(a)shows an R-S Flip-Flop Using NOR gate. It uses two -2
input NOR gates and connected in inverse parallel closed
loop as shown
• Symbol of R-S Flip-Flop:
• . Fig.(b)shows Symbol of R-S Flip-Flop and
• Following table shows an truth table of R-S flip-flop.
R S Y
0 0 No change/ Initial state
0 1 1 Set
1 0 0 Reset
1 1 Race/toggle/Not allowed/Not
defined/forbidden
4. Working of the R-S flip flop
• To see the working of the R-S flip flop firstly we see the truth table of the NOR gate
This is two input NOR gate its truth table
is shown as below.
Symbol of NOR gate
Truth table of two input NOR gate:-
The above truth table shows
that when any one of the input
of NOR gate is one its
output is zero. When any one
of the input is one we can’t see
for the second input because
if the second input is either 1or 0 the output of the NOR gate according to Boolean
expression A + B is 0.
This condition is called as an don’t care condition. Shown by ′ × ′ sign in below table of
truth table of NOR gate. Don’t care means if one of the input of NOR gate is 1 then its
output is 0 here not necessary to see the second input.
Inputs Outputs
A B Y= A + B
0 0 1
0 1 0
1 0 0
1 1 0
• Truth table of two input NOR gate using don’t
care condition ‘×’
Inputs Outputs
A B Y=
A + B
0 0 1
x 1 0
1
x 0
1
x 0
5. Working in Detail
consider initial state of RS flip-flop is Y=0 and Y = 1
1)when R=0, S=0 due to it inputs to NOR gate A are R=0 and
Y = 1, output of the NOR gate A=0.i.e. Y=0 input to NOR gate
B are Y=0 and S=0, output of the NOR gate B=1, i.e Y = 1 there
is no change in initial state.
2) when R=0, S=1 ,using don’t care condition as S=1the output
of NOR B is 0 i.e.Y = 0 .Then inputs to NOR gate A are are R=0
and Y = 0, output of the NOR gate A=1.i.e. Y=1 . Here state
is changed Y output changed to 1 i. e. Y output Sets.
3) when R=1, S=0 ,using don’t care condition as R=1the output
of NOR A is 0 i.e.Y = 0 .Then inputs to NOR gate B are are S=0
and Y = 0, output of the NOR gate B=1.i.e. Y=1 . Here state is
changed Y output changed to 0 i. e. Y output Resets.
4)When S=1,R=1 due to don’t care condition both NOR gate A
and B try to give their output to zero state which is not allowed
also it is called as toggle.
R S Y
0 0 No change/ Initial state
0 1 1 Set
1 0 0 Reset
1 1 Race/toggle/Not allowed/Not
defined/forbidden
6. R-S Flip Flop Using NAND Gate
R-S flip-flop can be constructed by using two NAND gates. The
output of each NAND-gate is connected to one of the inputs
of the other NAND-gate. S - (Set) and R - (Reset) inputs allows
to set or reset flip-flop
R-S Flip-Flop Using NAND Gate. Symbol of R/S F/F
Fig.5.25. shows an R-S Flip-Flop Using NAND gate. It uses two -2
input NAND gates and connected in closed loop as shown. Fig.
5.25(b)shows Symbol of R-S Flip-Flop and table 5.14shows an
truth table of R-S flip-flop.
Truth table of R-S Flip-Flop-
Working: To see the working of the R-S flip
flop firstly we see the truth table of the
NAND gate.
R S Y
0 0 Race/toggle/Not allowed/Not
defined/forbidden
0 1 1 Set
1 0 0 Reset
1 1 No change/ Initial state
7. Working of R-S Flip-Flop:-
NAND Gate-
This is two input NAND gate its truth table is shown as below. Truth
table of two input NAND gate.
Don’t Care Condition “X”
truth table shows that when any one of the input of NAND gate is
zero its output is one. When any one of the input is zero we can’t see
for the second input because if the second input is either 1or 0 the
output of the NAND gate according to Boolean expression A. B is 1.
This condition is called as an don’t care condition. Shown by ′ × ′ sign
A B Y= A. B
0 0 1
0 1 1
1 0 1
1 1 0
A B Y= A. B
X 0 1
X 1 1
1 X 1
1 1 0
8. Detail Working of R-S Flip Flop
Then consider initial state of RS flip-flop is Y=0 and Y = 1
• 1)when R=0, S=0 due to it inputs to NAND gate A and B has
output high (1) Hence Y becomes 1 and alsoYbecomes 1 state,
which is not allowed also it is called as toggle.
• 2) when R=0, S=1 ,using don’t care condition as R=0 the output
of NAND B is 1i.e.Y = 1 .Then inputs to NAND gate A are are
S=0 and Y = 1, output of the NAND gate A=1.i.e. Y=1 . Here
state is changed Y output changed to 1 i. e. Y output Sets.
• 3) when R=1, S=0 ,using don’t care condition as S=0 the output
of NAND B is 1i.e.Y = 1 .Then inputs to NAND gate A are
R=1 and Y = 1, output of the NAND gate A=0.i.e. Y=0 . Here
state is changed Y output changed to 0 i. e. Y output Reset
• 4)When S=1,R=1 due to it inputs to NAND gate A are R=1 and
Y = 1, output of the NAND gate A is A=0.i.e. Y=0 input to
NAND gate B are Y=0 and S=1, output of the NAND gate B=1,
i.e Y = 1 there is no change in initial state.
R S Y
0 0 Race/toggle/Not allowed/Not
defined/forbidden
0 1 1 Set
1 0 0 Reset
1 1 No change/ Initial state
9. R-S Clocked Flip- Flop
• The clocked flip-flop uses two AND gates A
and B at the input stage and common input
of both AND gate is named as Clock(CLK).
These two AND gate will supply an input S
and R to R-S F/F to operate when and only
when CLK is High.
• If clock is low using an don’t care condition
of AND gate R and S input becomes zero or
disabled to provide input to RS F/F.
• Diagram and truth table is shown in next CLK S R Q
0 X X No Change
1 0 0 No Change
1 0 1 0 Reset
1 1 0 1 set
1 1 1 Toggle
10. Level clocked R-S Flip Flop-
D-Flip- Flop- D - Latch
• A level clocked flip- flop is known as D-
Flip-Flop or D- Latch. It consist as two
AND Gates and Not gates are connected
to input of RS flip flop or only NOT gate is
extra to levelled RS flip-flop as shown in
below.
• There NOT is inserted between D and
input of B AND gate. It did not require
double rail data.
• Truth Table of D- F/F
CLK D Q
0 X NO Change/ Last State
1 0 0 Reset
1 1 1 Set
11. J-K flip-flop (J-K F/F)
• J-K F/F-
Diagram and symbol of j-k F/F
A J-K flip-flop is the refinements the RS flip-flop in that
the intermediate state of the RS flip-flop is defined in
the JK flip-flop. When logic 1 inputs are applied to
both J & K simultaneously, the flip-flop switches to its
complement state i.e. if Y = 1, it switches to Y = 0 and
vice versa.
The circuit is inactive when clock is LOW (0) and HIGH
(1) on its negative edge (↓) and output remains in the
last state or the initial state.
• A clocked J-K flip-flop is shown in following Fig. When J
= 0 and K = 0, both AND gates are disabled.
• Truth Table of J-K F/F :-
CLK J K Y
× 0 0 No change/ Initial state
↑ 0 1 1 Set
↑ 1 0 0 Reset
↑ 1 1 Race/ toggle / Not allowed /
12. Working of J-K Flip-Flop in Detail
• Where ‘×’is low state of CLOCK and ‘↑ ′ positive edge triggering.
• Above fig. shows the construction of J-K flip-flop and its logical
symbol in which three input AND A and B are used. Also the output
of the flip flop is feed back to the input again hence the output of
the flip flop is depend on input (i.e depend on the initial state).
• Working :-1)When CLK=0 then both AND gate A and B are disable,
hence there output are zero means S=0,R=0. Due to that the output
of the R-S flip-flop is no change i.e output of the J-K flip-flop
summarized in first state.
• 2)Now CLK=1(high),J=0,K=0 as the J and K are zero The one of the
input of both AND gate A and B is zero their output is 0.i.e. S=0 and
R=0 Due to that the output of the R-S flip-flop is no change i.e
output of the J-K flip-flop summarized in second state in above truth
table.
• 3)When CLk=1,J=0 and K=1, here taking in consideration the initial
states of the flip- flop. There are two possibilities,
a)When Y=0,Y = 1 initially or
b) When Y=1,Y = 0 initially or
• a) When Y=0,Y = 1 , AND gate A are Y = 1,J=0,CK=1 its
output is 0 hence S=0. inputs to AND gate B are
Y=0,CK=1,K=1 its output is 0 hence R=0. As S=0, R=0the
output of J-K flip-flop is zero means resets. i.e no change
means Y=0,Y = 1 (initial state.)
• b) When Y=1,Y = 0 initially inputs to AND gate A are Y =
0,J=0,CK=1 its output is 0 hence S=0. Then inputs to AND
gate B are Y=1,CK=1,K=1 its output is 1 hence R=1. As S=0,
R=1the output of J-K flip-flop resets,i.e Y=0,Y = 1
• From above discussion we see that when CLK =1,J=0 and
K=1then Y becomes 0 if it not 0 or output Y remain 0 if it is
already 0.It is total Reset.(Y=0).
13. Working of J-K Flip-Flop in Detail
• 4) When CLk=1,J=1 and K=0, here taking in consideration the
initial states of the flip- flop. There are two possibilities,
• a)When Y=0,Y = 1 initially or
• b) When Y=1,Y = 0 initially or
• a) When Y=0,Y = 1 initially, inputs to AND gate A are Y =
1,J=1,CK=1 its output is 1 hence S=1. Then inputs to AND gate B
are Y=0,CK=1,K=0 its output is 0 hence R=0. As S=1, R=0the
output of J-K flip-flop is 1 means sets state is changed to
Y=1,Y = 0
• b) When Y=1,Y = 0 initially inputs to AND gate A are Y =
0,J=1,CK=1 its output is 0 hence S=0. Then inputs to AND gate B
are Y=1,CK=1,K=0 its output is 0 hence R=0. As S=0, R=0the
output of J-K flip-flop no change or initial state Y=1,Y = 1 (flip-
flop is already set it remain as it is)
• From above discussion we see that when
CLk=1,J=1 and K=0then Y becomes 1 if it not 1 or output Y
remain 1 if it is already 1.It is total Set.(Y=1).
• 5) When CLk=1,J=1 and K=1, here taking in consideration the initial states
of the flip- flop. There are two possibilities,
• a)When Y=0,Y = 1 initially or
• b) When Y=1,Y = 0 initially or
• a) When Y=0,Y = 1 initially, inputs to AND gate A are Y = 1,J=1,CK=1 its
output is 1 hence S=1. Then inputs to AND gate B are Y=0,CK=1,K=0 its
output is 0 hence R=0. As S=1, R=0the output of J-K flip-flop is 1 means
changes state from Reset to Sets (initial state Y=0,Y = 1 change to
Y=1,Y = 0)
• b) When Y=1,Y = 0 initially inputs to AND gate A are Y = 0,J=1,CK=1 its
output is 0 hence S=0. Then inputs to AND gate B are Y=1,CK=1,K=1 its
output is 1 hence R=1. As S=0, R=1the output of J-K flip-flop resets means
changes state from Set to Resets (initial state Y=1,Y = 0 change to
Y=0,Y = 1)
• From above discussion we see that when CLk=1,J=1 and
K=1then Y changes to 1 if it initially 0 and vice versa. This condition is
called as Toggle also known as race around condition. These all states are
summarized in above truth table.
14. Master-Slave J-K flip flop-
• The Master-Slave flip flop is basically a combination
of two J-K flip flops connected in a series.
• Out of these, one acts as the 'Master' and the other
as 'Slave’.
• The Master is positive edge triggered while the slave
is negative edge triggered.
• The output of Master flip flop is connected to the two
inputs of slave flip flop. Output of this slave is fed
back to inputs of the master flip flop.
• In addition to these two flip flops, the circuit also
includes an inverter. The inverter is connected to
clock pulse in such a way that the inverted clock pulse
is given to the slave flip flop.
• In other words if clock pulse is 0 for master flip flop,
then clock pulse is I for the slave. And when clock
pulse is I for the master, it will be 0 for the slave.
• The logical circuit and symbol are shown in Fig. (1.21)
below. Master slave J-K flip flops are used in counters.
15. Master-Slave J-K flip flop-
• Working of J/K M/S Flip- Flop-
• There are five inputs namely J, K, CLK, PR (Preset) and
CLR (Clear). When PR = 0 and CLR = 0, a race condition
is produced.
• A low preset causes presetting (Q = 1 ) and a low clear
causes resetting (Q = 0). Therefore, both PR and CLR
cannot be low at the same time. Normally PR and CLR
are kept at a high voltage V when they are inactive.
• If J = 0 and K = 0, both flip flops remain in their last
states irrespective of the clock pulses.
• If J = 0 and K = 1, on the leading edge of clock pulse,
the master flip flop resets. The high Q output of master
goes to K input of the slave. Therefore, on arrival of
clock's negative edge, the slave resets. Hence, output
Q = 0.
• Similarly, if J = 1 and K = 0 we get output Q = 1. When J
= 1 and K = 1, the master toggles on the positive clock
edge and slave toggles on negative clock edge. Thus
the slave copies the action of the master flip flop on
negative edge of each clock pulse.
• . Hence, the name Master-Slave flip flop. The truth table is as
given below
• Truth Table of Master – slave J-K Flip-flop.
INPUT OUTPT
PR CLR CLK J K Q
0 0 X X X RACE/
Toggle
0 1 X X X 1
1 0 X X X 0
1 1 0 0 0 Last State
1 1 ⨅ 0 0 Last state
1 1 ⨅ 0 1 0 (RESET)
1 1 ⨅ 1 0 1 (SET)
1 1 ⨅ 1 1 TOGGLE
N.A
