Computer Organization and Design

1. Computer Organization and
Design
V SEM BCA

2. Introduction
• What is a Digital Computer?
• A device capable of solving problems by processing information in discrete form.
It operates on data, including magnitudes, letters, and symbols, that are expressed
in binary code—i.e., using only the two digits 0 and 1.
• Computer architecture - deals with the specification of the instruction set and the
hardware units that implement the instruction.
• Computer hardware - consists of electronic circuits, displays, magnetic and optic
storage media and also the communication facilities.

3. Basic Structure of a digital computer
Main components of a computer
- I/O unit, CPU, Memory unit ,
Arithmetic & logical unit,
Control unit.

5. General System Architecture
• In Computer Architecture, the General System Architecture is divided into two
major classification units
• Store Program Control Concept :In this the instructions are stored in computer
memory to enable it to perform a variety of tasks in sequence or intermittently.
• Flynn's Classification of Computer :M.J. Flynn proposed a classification for
the organization of a computer system by the number of instructions and data
items that are manipulated simultaneously.
• The sequence of instructions read from memory constitutes an instruction
stream.
• The operations performed on the data in the processor constitute a data stream.

6. Types of Architecture
• Von Neumann Architecture [Princeton Architecture]
• Harvard Architecture

7. Von Neuman Architecture
• John von Neumann in 1945.
• Based on the stored-program computer concept, where instruction
data and program data are stored in the same memory.
• Von Neumann-based computer
• Ø Uses a single processor
• Ø Uses one memory for both instructions and data
• Ø Executes programs following the fetch-decode-execute cycle

8. Von-Neuman architecture cont….
Components
• Central Processing Unit -
ALU,CU,Registers -high-
speed storage areas in the
CPU
(AC,MAR,MDR,CIR,PC)
• Buses - means by which
information is shared between
the registers (Address
bus,Data bus, Control bus)
• Memory Unit (RAM,ROM)

9. Basic Structure of a CPU

10. Von Neuman Bottleneck
• In Von Neumann Architecture instructions can only be done one at a time and can
only be carried out sequentially. Both of these factors hold back the competence of
the CPU - referred as Von Neumann – Bottleneck.

11. Harvard Architecture
• This architecture contains separate storage and separate buses for instruction and
data. It was basically developed to overcome the bottleneck of Von Neumann
Architecture.
• The advantage of having separate buses for instruction and data is that CPU can
access instructions and read/write data at the same time.

12. Harvard Architecture
• In Harvard architecture there are separate buses for both instruction and
data.
• Types of Buses
• Data Bus: It carries data among the main memory system, processor and
I/O devices.
• Data Address Bus: It carries the address of data from processor to main
memory system.
• Instruction Bus: It carries instructions among the main memory system,
processor and I/O devices.
• Instruction Address Bus: It carries the address of instructions from
processor to

13. Difference between Von-Neuman Architecture and
Harvard Architecture
Von Neuman Architecture Harvard Architecture

14. • The instructions are stored in computer memory in the same
manner that data is stored.
• The control unit interprets these instructions and uses the
operations code to determine the sequences of
microoperations that must be performed to execute the
instruction.
Microoperations

16. Accumulator (AC)
Computers that have a single-processor register usually
assign to it the name accumulator and label it AC. The
operation is performed with the memory operand and the
content of AC.

17. Computer Instruction
• They are set of machine language instructions that a particular processor
understands and executes. A computer performs tasks on the basis of the
instruction provided.
• A computer instruction is a binary code that specifies a sequence of
microoperations for the computer. Instruction codes together with data are stored
in memory.
• The computer reads each instruction from memory and places it in a control
register. The control then interprets the binary code of the instruction and proceeds
to execute it by issuing a sequence of microoperations.
• Every computer has its own unique instruction set.

18. Instruction code
• An instruction code is a group of bits that instruct the computer to perform a
specific task.
• It is usually divided into parts, each having its own particular
interpretation.
• An instruction comprises of groups called fields.
• These field include:
• 1. Operation code (Opcode) : field which specifies the operation to be
performed
• 2. Address field : contains the location of the operand, i.e., register or
memory location
• 3. Mode field : specifies how the operand will be located.

19. • The most basic part of an instruction code is its operation part. The operation code
of an instruction is a group of bits that define such operations as add, subtract,
multiply, shift, and complement.
• The operation part of an instruction code specifies the operation to be performed.
This operation must be performed on some data stored in processor registers or in
memory.
• An instruction code must therefore specify not only the operation but also the
registers or the memory words where the operands are to be found, as well as the
register or memory word where the result is to be stored.
• Memory words can be specified in instruction codes by their address.

20. ADDRESSING MODES
• The address field of an instruction can represent either
• – Direct address: the address in memory of the data to use (the address of
the operand),
• or – Indirect address: the address in memory of the address in memory of
the data to use.
• Effective Address (EA) – The address, that can be directly used without
modification to access an operand for a computation-type instruction, or
as the target address for a branch-type instruction

21. Stored Program Organization
• The simplest way to organize a computer is to have one processor register and an
instruction code format with two parts. The first part specifies the operation to be
performed and the second specifies an address.
• The memory address tells the control where to find an operand in memory. This
operand is read from memory and used as the data to be operated on together with
the data stored in the processor register.
• Instructions are stored in one section of memory and data in another. For a
memory unit with 4096 words we need 12 bits to specify an address since 2^12 =
4096.
• If we store each instruction code in one 16-bit memory word, we have available
four bits for the operation code (abbreviated opcode) to specify one out of 16
possible operations, and 12 bits to specify the address of an operand.
• The control reads a 16-bit instruction from the program portion of memory. It uses
the 12-bit address part of the instruction to read a 16-bit operand from the data
portion of memory. It then executes the operation specified by the operation code.

22. • Computers that have a single-processor register usually
assign to it the name accumulator and label it AC. The
operation is performed with the memory operand and the
content of AC.
• If an operation in an instruction code does not need an
operand from memory, the rest of the bits in the
instruction can be used for other purposes. For example,
operations such as clear AC, complement AC, and
increment AC operate on data stored in the AC register.
• They do not need an operand from memory. For these
types of operations, the second part of the instruction
code (bits 0 through 11) is not needed for specifying a
memory address and can be used to specify other
operations for the computer i.e specifying other
operations.

23. Indirect Address
• It is sometimes convenient to use the address bits of an instruction code not as an
address but as the actual operand. When the second part of an instruction code
specifies an operand, the instruction is said to have an immediate operand.
• When the second part specifies the address of an operand, the instruction is said to
have a direct address.
• This is in contrast to a third possibility called indirect address, where the bits in
the second part of the instruction designate an address of a memory word in which
the address of the operand is found.
• One bit of the instruction code can be used to distinguish between a direct and an
indirect address.
• The memory word that holds the address of the operand in an indirect address
instruction is used as a pointer to an array of data. The pointer could be placed in a
processor register instead of memory as done in commercial computers.

25. • As an illustration of this configuration, consider the instruction code format shown
in Fig. 5-2(a). It consists of a 3-bit operation code, a 12-bit address, and an
indirect address mode bit designated by I.
• The mode bit is 0 for a direct address and 1 for an indirect address.
• A direct address instruction is shown in Fig. 5-2(b). It is placed in address 22 in
memory. The I bit is 0, so the instruction is recognized as a direct address
instruction. The opcode specifies an ADD instruction, and the address part is the
binary equivalent of 457. The control finds the operand in memory at address 457
and adds it to the content of AC.
• The instruction in address 35 shown in Fig. 5-2( c) has a mode bit I = 1. Therefore,
it is recognized as an indirect address instruction. The address part is the binary
equivalent of 300. The control goes to address 300 to find the address of the
operand. The address of the operand in this case is 1350. The operand found in
address 1350 is then added to the content of AC.
• The indirect address instruction needs two references to memory to fetch an
operand. The first reference is needed to read the address of the operand; the
second is for the operand itself.
• We define the effective address to be the address of the operand in a computation-
type instruction or the target address in a branch-type instruction. Thus the
effective address in the instruction of Fig. 5-2(b) is 457 and in the instruction of
Fig 5-2( c) is 1350.

27. Computer Registers
• Computer instructions are normally stored in consecutive memory
locations and are executed sequentially one at a time. The control
reads an instruction from a specific address in memory and executes it.
It then continues by reading the next instruction in sequence and
executes it, and so on.
• This type of instruction sequencing needs a counter to calculate the
address of the next instruction after execution of the current instruction
is completed. It is also necessary to provide a register in the control
unit for storing the instruction code after it is read from memory.
• The computer needs processor registers for manipulating data and a
register for holding a memory address.

29. • The memory unit has a capacity of 4096 words and each word contains 16 bits.
Twelve bits of an instruction word are needed to specify the address of an operand.
• This leaves three bits for the operation part of the instruction and a bit to specify a
direct or indirect address.
• The data register (DR) holds the operand read from memory.
• The accumulator (AC) register is a general purpose processing register.
• The instruction read from memory is placed in the instruction register (IR).
• The temporary register (TR) is used for holding temporary data during the
processing.
• The memory address register (MAR) has 12 bits since this is the width of a
memory address.

30. • The program counter (PC) also has 12 bits and it holds the address of the next
instruction to be read from memory after the current instruction is executed.
• The PC goes through a counting sequence and causes the computer to read
sequential instructions previously stored in memory. Instruction words are read
and executed in sequence unless a branch instruction is encountered.
• A branch instruction calls for a transfer to a nonconsecutive instruction in the
program. The address part of a branch instruction is transferred to PC to become
the address of the next instruction.
• To read an instruction, the content of PC is taken as the address for memory and a
memory read cycle is initiated. PC is then incremented by one, so it holds the
address of the next instruction in sequence.
• Two registers are used for input and output.
• The input register (INPR) receives an 8-bit character from an input device.
• The output register (OUTR) holds an 8-bit character for an output device.

31. Common bus structure
• The registers in the Basic Computer are connected using a bus
• This gives a savings in circuitry over complete connections between
registers

32. Bus Structure in Computer Architecture
• A system bus has typically from fifty to hundreds of distinct lines where each line
is meant for a certain function. These lines can be categories into three functional
groups i.e., data lines, address lines, and control lines. Let us discuss them one by
one each.

33. • 1. Data Lines
• Data lines coordinate in transferring the data among the system components. The
data lines are collectively called data bus. A data bus may have 32 lines, 64 lines,
128 lines, or even more lines. The number of lines present in the data bus defines
the width of the data bus.
• Each data line is able to transfer only one bit at a time. So the number of data lines
in a data bus determines how many bits it can transfer at a time. The performance
of the system also depends on the width of the data bus.

34. • Address Bus
• The content of the address lines of the bus determines the source or destination
of the data present on the data bus. The number of address lines together is
referred to as address bus. The number of address lines in the address bus
determines its width.
• The width of the address bus determines the memory capacity of the system. The
content of address lines is also used for addressing I/O ports. The higher-order bits
bits determine the bus module and the lower ordered bits determine the address
of memory locations or I/O ports.
• Whenever the processor has to read a word from the memory it simply places the
the address of the corresponding word on the address line.

35. • 3. Control Lines
• The address lines and data lines are shared by all the components of the system so
there must some means to control the use and access of data and address lines. The
control signals placed on the control lines control the use and access to address
and data lines of the bus. The control signal consists of the command and timing
information. Here the command in the control signal specify the operation that has
to be performed. And the timing information over the control signals specify till
when the data and address information is valid .
• If a component connected to the bus wishes to send data to another connected
component, it first has to acquire control over the bus, and then it can transfer the
data to another component over the bus. The same happen when a component
request data from another component.
• During the transfer of data between two components, one component act as a
master and other act as a slave. The device initiating the data transfer is referred to
as master and usually, it is a processor, or sometimes it may be some other device
or component. The component addressed by the master component is referred to
as a slave.

36. • The control lines include the lines for:
• Memory Write: This command causes the data on the data bus to be placed over the addressed
memory location.
• Memory Read: This command causes the data on the addressed memory location to be placed on
the data bus.
• I/O Write: The command over this control line causes the data on the data bus to be placed over
the addressed I/O port.
• I/O Read: The command over this control line causes the data from the addressed I/O port to be
placed over the data bus.
• Transfer ACK: This control line indicates the data has been received from the data bus or is
placed over the data bus.
• Bus Request: This control line indicates that the component has requested control over the bus.
• Bus Grant: This control line indicates that the bus has been granted to the requesting component.
• Interrupt Request: This control line indicates that interrupts are pending.
• Interrupt ACK: This control line provides acknowledgment when the pending interrupt is
serviced.
• Clock: This control line is used to synchronize the operations.
• Reset: The bit information issued over this control line initializes all the modules.

37. Common Bus Structure

38. • S2S1S0: Selects the register/memory that would use the bus
• LD (load): When enabled, the particular register receives the data from
the bus during the next clock pulse transition
• E (extended AC bit): flip-flop holds the carry
• DR, AC, IR, and TR: have 16 bits each
• AR and PC: have 12 bits each since they hold a memory address

39. • When AR or PC receives information from the bus, only the 12 least
significant bits are transferred into the register
• INPR and OUTR: communicate with the eight least significant bits in
the bus
• INPR: Receives a character from the input device (keyboard,…etc)
which is then transferred to AC
• OUTR: Receives a character from AC and delivers it to an output
device (say a Monitor)

40. • Five registers have three control inputs: LD (load), INR (increment), and CLR
(clear)
• The input data and output data of the memory are connected to the common bus
• But the memory address is connected to AR
• Therefore, AR must always be used to specify a memory address
• Register  Memory: Write operation
• Memory  Register: Read operation

41. Computer Instructions
• A computer has programs stored in its RAM in the form of 1s and 0s
that are interpreted by the CPU as instructions. One word of RAM
includes one instruction in the machine language.
• These instructions are loaded to the CPU one at a time, where it
receives decoded and implemented. A basic computer has three
instruction code formats such as the memory reference instruction, the
register reference instruction, and the input-output instruction format.
• Each format has 16 bits. The operation code (opcode) part of the
instruction contains three bits and the meaning of the remaining 13
bits depends on the operation code encountered.

42. • Memory Reference Instruction
• A memory-reference instruction uses 12 bits to specify an address and one bit to
determine the addressing mode I. I is the same as 0 for direct address and to 1 for
indirect address.
• Register Reference Instruction
• The register reference instructions are identified by the operation code 111 with a
0 in the leftmost bit (bit 15) of the instruction. It determines an operation on or a
test of the AC register. An operand from memory is not required because the
additional 12 bits are used to determine the operation or test to be implemented.

43. • Input-Output Instruction
• An input-output instruction does not require a reference to memory and is
identified by the operation code 111 with a 1 in the leftmost bit of the instruction.
The remaining 12 bits can determine the type of input-output operation or test
implemented.
• The type of instruction is identified by the computer control from the four bits in
positions 12 through 15 of the instruction. If the three opcode bits in positions 12
through 14 are not similar to 111, the instruction is a memory-reference type and
the bit in position 15 is taken as the addressing mode I.
• If the 3-bit opcode is similar to 111, the control then examines the bit in position
15. If this bit is 0, the instruction is a register-reference type. If the bit is 1, the
instruction is an input-output type.

45. Instruction Cycle
• A program residing in the memory unit of the computer consists of a sequence of
instructions.
• The program is executed in the computer by going through a cycle for each
instruction.
• Each instruction cycle in turn is subdivided into a sequence of subcycles or
phases.
• In the basic computer each instruction cycle consists of the following phases:
• 1. Fetch an instruction from memory.
• 2. Decode the instruction.
• 3. Read the effective address from memory if the instruction has an indirect
address.
• 4. Execute the instruction
• After the following four procedures are done, the control switches back to the first
step and repeats the similar process for the next instruction. Therefore, the cycle
continues until a Halt condition is met. The figure shows the phases contained in
the instruction cycle.

47. 1. Initiating Cycle
In this phase, the computer system boots up, and the operating system loads in the main memory (read-
only memory) of the central processing unit. It immediately begins when the computer system starts.
2. Fetching of Instruction
The fetching of instruction is the first phase. The fetch instruction is common for each instruction
executes in a central processing unit. In this phase, the central processing unit sends the PC to MAR and
then sends the READ command into a control bus. After sending a read command on the data bus, the
memory returns the instruction, which is stored at that particular address in the memory. Then, the CPU
copies data from the data bus into MBR and then copies the data from MBR to registers. After all this,
the pointer is incremented to the next memory location so that the next instruction can be fetched from
memory.

48. • Decoding of Instruction
• The decoding of instruction is the second phase. In this phase, the CPU determines
which instruction is fetched from the instruction and what action needs to be
performed on the instruction. The opcode for the instruction is also fetched from
memory and decodes the related operation which needs to be performed for the
related instruction.
• 4. Read of an Effective Address
• The reading of an effective address is the third phase. This phase deals with the
decision of the operation. The operation can be of any type of memory type non-
memory type operation. Memory instruction can be categorized into two
categories direct memory instruction and indirect memory instruction.
• 5. Executing of Instruction
• The executing of instruction is the last phase. In this stage, the instruction is
finally executed. The instruction is executed, and the result of the instruction is
stored in the register. After the execution of an instruction, the CPU prepares itself
for the execution of the next instruction. For every instruction, the execution time
is calculated, which is used to tell the processing speed of the processor.

49. The flowchart presents an initial configuration for the
instruction cycle and shows how the control
determines the instruction type after the decoding.
If D7 = 1, the instruction must be register-reference
or input-output type. If D7 = 0, the operation code
must be one of the other seven values 110, specifying
a memoryreference instruction. Control then inspects
the value of the first bit of the instruction, which now
available in flip-flop I.
If D7 = 0 and I = 1, we have a memory-reference
instruction with an indirect address. It is then
necessary to read the effective address from memory.

50. • The three instruction types are subdivided into four separate paths. The selected
operation is activated with the clock transition associated with timing signal
T3.This can be symbolized as follows: D’7 I T3: AR
• M [AR] D’7 I’ T3: Nothing D7 I’ T3: Execute a register-reference instruction
D7 I T3: Execute an input-output instruction
• When a memory-reference instruction with I = 0 is encountered, it is not
necessary to do anything since the effective address is already in AR.
• However, the sequence counter SC must be incremented when D’7 I T3 = 1, so
that the execution of the memory-reference instruction can be continued with
timing variable T4.
• A register-reference or input-output instruction can be executed with the click
associated with timing signal T3. After the instruction is executed, SC is cleared to
0 and control returns to the fetch phase with T0 =1. SC is either incremented or
cleared to 0 with every positive clock transition

51. Importance of Instruction Cycle
• It is a set of steps that help to understand the flow of instruction. By
the instruction cycle, the end to end the flow of instructions can be
visualized in the computer processor.
• It is common for all instruction set it needs to properly understand so
that all the operations can be performed easily.
• By the instruction cycle, the processing time of the program can be
easily calculated, which helps to determine the speed of the processor.
• As the speed of the processor tells how many instructions can be
simultaneously executed in the central processing unit.

52. Input-Output and Interrupt
• A computer can serve no useful purpose unless it communicates with the external environment.
Instructions and data stored in memory must come from some input device. Computational results
must be transmitted to the user through some output device.
• Commercial computers include many types of input and output devices. To demonstrate the most
basic requirements for input and output communication, we will use as an illustration a terminal
unit with a keyboard and printer.
• Input-Output Configuration
• The terminal sends and receives serial information. Each quantity of information has eight bits of
an alphanumeric code. The serial information from the keyboard is shifted into the input register
INPR.
• The serial information for the printer is stored in the output register OUTR.
• These two registers communicate with a communication interface serially and with the AC in
parallel. The input-output configuration is shown in Fig. 5-12. The transmitter interface receives
serial information from the keyboard and transmits it to INPR.
• The receiver interface receives information from OUTR and sends it to the printer serially.

53. • FGI is set to 1 when a new information is available in
the input device and is cleared to 0 when the
information is accepted by the computer.
• If FGO is set to 1, then this means that the computer
can send out the information from AC. If it is 0, then
the output device is busy and the computer has to wait!
• INPR and OUTR communicate with a communication
interface serially and with the AC in parallel. They
hold an 8-bit alphanumeric information
• I/O devices are slower than a computer system  we
need to synchronize the timing rate difference
between the input/output device and the computer.
• FGI: 1-bit input flag (Flip-Flop) aimed to control the
input operation
• FGI is set to 1 when a new information is available in
the input device and is cleared to 0 when the
information is accepted by the computer
• FGO: 1-bit output flag used as a control flip-flop to
control the output operation
• If FGO is set to 1, then this means that the computer
can send out the information from AC. If it is 0, then
the output device is busy and the computer has to wait!
• FGI = Flag flip flop respect to input

54. • The process of input information transfer:
Initially, FGI is cleared to 0
An 8-bit alphanumeric code is shifted into INPR (Keyboard key
strike) and the input flag FGI is set to 1
As long as the flag is set, the information in INPR cannot be
changed by another data entry
The computer checks the flag bit; if it is 1, the information from
INPR is transferred in parallel into AC and FGI is cleared to 0.
Once the flag is cleared, new information can be shifted into INPR
by the input device (striking another key)

55. • The process of outputting information:
Initially, the output flag FGO is set to 1
The computer checks the flag bit; if it is 1, the information from
AC is transferred in parallel to OUTR and FGO is cleared to 0
The output accepts the coded information (prints the corresponding
character)
When the operation is completed, the output device sets FGO back
to 1.
The computer does not load a new data information into OUTR
when FGO is 0, because this condition indicates that the output
device is busy to receive another information at the moment!!

56. Input-Output Instructions
• The I/O devices are given specific addresses. The processor similarly
views the I/O operations as memory operations. It concerns commands
that include the address for the device.
• The I/O instructions are needed for the following objectives −
• It is used to analyzing flag bits.
• It can transfer data to or from the AC register.
• It can controlling interrupts.
• The I/O instructions carry the opcode as 1111. They are recognized
through the control when D7 = 1 and I=1. The operation to be executed
is determined by the different remaining bits.

57. • There are various I/O Instructions which are shown in the table −
Each control function needs a Boolean relation
D7IT3, which we designate for convenience by the
symbol p. The control function is distinguished by
one of the bits in IR(6-11). By assigning the
symbol B, to bit i of IR, all control functions can be
denoted by pB; for i = 6 though II. The sequence
counter SC is cleared to 0 when p = D71T3 = I.

58. Interrupts
• An interrupt in computer architecture is a signal that requests the processor to suspend its current
execution and service the occurred interrupt. To service the interrupt the processor executes the
corresponding interrupt service routine (ISR). After the execution of the interrupt service routine,
the processor resumes the execution of the suspended program.
• Interrupts can be of two types of hardware interrupts and software interrupts.

59. Types of Interrupts
• The interrupts can be various type but they are basically classified into hardware
interrupts and software interrupts.
• 1. Hardware Interrupts
• If a processor receives the interrupt request from an external I/O device it is
termed as a hardware interrupt.
• Hardware interrupts are further divided into maskable and non-maskable interrupt.
• Maskable Interrupt: The hardware interrupt that can be ignored or delayed for
some time if the processor is executing a program with higher priority are termed
as maskable interrupts.
• Non-Maskable Interrupt: The hardware interrupts that can neither be ignored nor
delayed and must immediately be serviced by the processor are termed as non-
maskeable interrupts.

60. • 2. Software Interrupts
• The software interrupts are the interrupts that occur when a condition is met or a
system call occurs.
• Interrupt Cycle
• A normal instruction cycle starts with the instruction fetch and execute. But, to
accommodate the occurrence of the interrupts while normal processing of the
instructions, the interrupt cycle is added to the normal instruction cycle as shown
in the figure below.

61. • After the execution of the current instruction, the processor verifies the interrupt
signal to check whether any interrupt is pending. If no interrupt is pending then
the processor proceeds to fetch the next instruction in the sequence.
• If the processor finds the pending interrupts, it suspends the execution of the
current program by saving the address of the next instruction that has to be
executed and it updates the program counter with the starting address of the
interrupt service routine to service the occurred interrupt.
• After the interrupt is serviced completely the processor resumes the execution of
the program it has suspended.

62. • The interrupt is a signal emitted by hardware
or software when a process or an event needs immediate
attention.
• Program interrupt defines the transfer of program control
from a currently running program to another service program
as a result of an external or internal created request.
Program Interrupt

63. • The process of communication just described is referred to as
Programmed Control Transfer
• The interrupt facility can be enabled or disabled via a flip-flop called
IEN
• The interrupt enable flip-flop IEN can be set and cleared with two
instructions (IOF, ION):
• IOF: IEN  0 (the computer cannot be interrupted) interrupt
enabled off
• ION: IEN  1 (the computer can be interrupted) interrupt
enabled on.
• Another flip-flop (called the interrupt flip-flop R) is used in the
computer’s interrupt facility to decide when to go through the
interrupt cycle.

65. BUN – Branch unconditionally

66. What is Interrupt Latency?
• As we know to service the occurred to interrupt the processor suspends the
execution of the current program and save the details of the program to maintain
the integrity of the program execution. The modern processor store the minimum
information that will be needed by the processor to resume the execution of the
suspended program. Still, the saving and restoring of information from memory
and registers which involve memory transfer increase the execution time of the
program.
• Transfer of memory also occurs when the program counter is updated with the
starting address of the interrupt service routine. This memory transfer causes the
delay between the time the interrupt was received and the processor starts
executing the interrupt service routine. This time delay is termed as interrupt
latency.

67. Design of a basic computer
• A basic computer consists of the following hardware components.
1.A memory unit with 4096 words of 16 bits each
2.Registers: AC (Accumulator), DR (Data register), AR (Address register), IR
(Instruction register), PC (Program counter), TR (Temporary register), SC
(Sequence Counter), INPR (Input register), and OUTR (Output register).
3.Flip-Flops: I, S, E, R, IEN, FGI and FGO
4.Two decoders: a 3 x 8 operation decoder and 4 x 16 timing decoder
5.A 16-bit common bus
6.Control Logic Gates
7.The Logic and Adder circuits connected to the input of AC.