Talked at ITC-CSCC2015

1. Generalized Isomorphism
between Synchronous Circuits
and State Machines
Shunji Nishimura
July 1, 2015 ITC-CSCC

2. 2
Motivation
Category theory
Great successes in software science
ex. programming semantics
(modeling)
might be in hardware
object
object
object

3. 3
Known isomorphism
f
D-FlipFlop synchronous circuit and state machine
Low LowHigh
D-FF
f
next
equaldiscrete
sampling
circuit
SM

4. 4
(part of) Our isomorphism
D-Latch synchronous circuit and state machine
a0 a1 a2 a3
a0 a1 a2 a3
f
D-Latch
f
next
equal
circuit
SM
time structure
transformation

5. Agenda
(0) Modeling on category theory
(1) Evaluation operator
(2) Comprehensive Latches
(3) Transformation of time structure
(1)
(2)
(3)

6. 6
Category:
signal as:
Modeling on category [1/3]
object
object
object
signal
value
signal
value
signal
value
time as:
time
point
time
point
time
point

7. 7
A B
SS := functor A × S → B × SA circuit:
An evaluation pattern := functor time T → signal A
Modeling on category [2/3]
category A
functor
category B
Functor:
mapping between categories

8. Natural transformation:
mapping between functors
8
Modeling on category [3/3]
category
Natural
transformation
category
functor F
functor G
will be used for our transformation of time structure.

9. (Agenda)
(0) Modeling on category theory
(1) Evaluation operator
(2) Comprehensive Latches
(3) Transformation of time structure
(1)
(2)
(3)

10. 10
Evaluation operator [1/3]
A
A×S
T B
B×S
a
f
a ▷ f
f
A B
SS
time
evaluation
result
Define operator ▷ which determines evaluation results.
evaluation
pattern
circuit
= a ▷ fviz.
a

11. Time (= category) for evaluation
Encountering problem
Intend to : (transit t0 → t1 → t2),
but in fact : (exists t0 → t2).
11
: non-deterministic branching
t0 t1 t2
t0 t1 t2
compositon
Evaluation operator [2/3]
: joining together
Consider time structure τ of time T as:
τ ⊂ { morphisms of T } a ▷ f
τ

12. 12
τ τ
t0 t1
f s0
fs0
= f
next
= f
state machine
combinational
circuit
Evaluation operator [3/3]
Similar to the state machine evaluation
 To imitate logic simulation, iterative calculation
is described by identity morphism.

13. (Agenda)
(0) Modeling on category theory
(1) Evaluation operator
(2) Comprehensive Latches
(3) Transformation of time structure
(1)
(2)
(3)

14. 14
？
Comprehensive Latches [1/2]
order reversal of
previous/current
signal
rejected accepted
aim to build the most general latches/FFs
rejected accepted
τ
redundant
(premised on )
corresponding to
enable state of
D-Latchs
corresponding to
disable state of
D-Latchs

15. 15
C
A
A A
A
A
1 2 n
Comprehensive Latch : (C×A)×An → A×An
= C×An+1 → An+1
input state output state
Comprehensive Latches [2/2]
Definiton: serial connection of
(function to) the previous units

16. (Agenda)
(0) Modeling on category theory
(1) Evaluation operator
(2) Comprehensive Latches
(3) Transformation of time structure
(1)
(2)
(3)

17. 17
Transformation of time structure [1/2]
C×Tn+1
T T
(clock) ck
ρ
id(identity)
C×T
Tn+1
ck×id ▷ ρ
τ
comprehensive
latch
τ: time structure
ρ:
T T
(Natural
transformation)
id
Renewed time structure is defined as:

18. 18
t0
ck
τ
(Low enable)
=
ρ=
=
=
ex.
τ
=
t1 t2 t3 t4 t5 t6
t0 t0 t0 t3 t4 t4 t4
t0 t1 t2 t3 t4 t5 t6
D-Latch
throughkeep
=( id )
∴
Transformation of time structure [2/2]
ck×id ▷ρ
natural transformation

19. 19
Theorem: isomorphism [1/2]
ρ synchronous circuit and state machine
(ρ: comprehensive latch)
f
f
next
equaltime structure
transformation
ρ
a0 a1 a2
τ
=
=
ck
pattern =
a0 a1 a2
=
=pattern
along
with
along
with

20. The two functors in the center
are the same.
20
C×A×Sn+1
T B
B×Sn+1
clock ck
fρ
a
A
A×S
B×S
=
evaluation
pattern
circuit f
f
ρ
C
A
S
Sn
B
S
Sn
ck×a ▷ fρ
τ
a ▷ fa
comprehensive latch
τ: time structure
ρ:
Theorem: isomorphism [2/2]
C×A

21. 21
Conclusion
Generalized theory was acquired
using category theory.
A common modeling of circuits and
state machines is presented.
A generalized concept of latches/FFs
is also presented.
A state machine corresponding to a D-
Latch synchronous circuit is available.