CV

1. Namathoti Siva
Roll No. 144102009
M.Tech – VLSI
Department of Electronics& Electrical Engineering
Indian Institute of Technology Guwahati
+91-9957721953
namathoti@iitg.ernet.in
sivaram.namathoti@gmail.com
Degree Institute CGPA Year
M.Tech Indian Institute of Technology Guwahati, Assam. 8.62/10 2014-2016
B.Tech – ECE
Senior Secondary - MBiPC
Rajiv Gandhi University of Knowledge Technologies
Nuzvid Campus, AP.
Rajiv Gandhi University of Knowledge Technologies
Nuzvid Campus, AP.
8.26/10
9.32/10
2010-2014
2008-2010
Secondary Z.P.H School, Revendrapadu, AP. 90.83% March, 2008
PROJECTS
DESIGN OF A DEDICATED MULTI-PROCESSOR USING FPGA FOR REAL TIME HIGH FREQUENCY TRADING
(HFT) APPLICATIONS
JUL’15-
TILL
Dr. Gaurav Trivedi
Key responsibilities:
 Design of hardware TCP/IP protocol stack to receive (send) packets from (to) the NSE server.
 Create a packet decoder unit that decodes the incoming packet and moves it to the core processor where a
strategy is applied on the incoming packet and required action is taken up.
 Packet encoder module that packs all the packet fields and forwards it to front end IP core if the strategy is
met by the incoming packet.
 Design of core 32-bit processor module to process incoming packets and apply the strategy to the packets.
IMPLEMNETED AN IEEE PAPER TITLED “LOW POWER AND AREA-EFFICIENT CARRY SELECT ADDER” OCT’14-NOV’’14
Dr. Nagarjuna Nallam
 This IEEE paper proposes that existing Carry Select Adder used in data processing processors can be modified to
significantly reduce the power and area. The Adder was implemented using Verilog HDL& implemented in Xilinx
Spartan 3E kit. (IEEE transactions on very large scale integration(VLSI)systems, vol.20, no.2, feb’2012)
DESIGN& IMPLEMENTATION OF SINGLE CYCLE, 32 BIT MIPS PROCESSOR ON XILINX VERTEX-6 ML605
EVALUATION KIT
JAN’15-APR’15
Dr. Gaurav Trivedi
 Design of processor data path and control unit and integrating them into a single module.
 Design of UART receiver module to load the instructions into the Instruction ROM for testing the processor on
FPGA.
ADIABATIC TECHNIQUE FOR ENERGY EFFICIENT LOGIC CIRCUIT DESIGN JUL’13-APR’14
Mr. Dheeraj Kumar
 To minimize the energy consumption in conventional CMOS circuits through adiabatic technique. In analysis,
two logic families, ECRL (Energy efficient charge recovery logic), PFAL (Positive feedback adiabatic logic) are
compared with conventional CMOS logic for basic logic gates and ROM subsequently.
M.TECH COURSE PROJECTS
 Design of 32 bit CORDIC calculator using pipelining in Verilog HDL.
 IEEE 754 single precision Floating Point Multiplier and Divider implementation in Verilog HDL.
 Design of single precision Floating Point Canonical Signed Digit (CSD) multiplier in Verilog HDL.

2. Page 2
ACHIEVEMENTS
 Figured in the list of top 1% students of SSC 2008, AP.
TECHNICAL PROFICIENCY
 Programming Languages : C, Python
 Technical Tools : Xilinx ISE, Mentor Graphics, Ngspice, Altera Quartus II, ModelSim
 Hardware Languages : Verilog HDL
 Hardware kits : Xilinx Vertex-6, Spartan 3E, Krypton CPLD v1.2
RELEVANT COURSES
Digital Logic and Circuit design Digital IC Design
Digital design using FPGAs and CPLDs VLSI System Design
VLSI DSP Computer Architecture
Hardware and software interface Embedded systems
POSITIONS OF RESPONSIBILITY
STUDENT PLACEMENT COORDINATOR (M.Tech) JUL’15-TILL
 To actively engage in establishing contacts with renowned and elite MNC’s through proper channels and thus
substantiating my efforts towards improving placement prospects at the institute.
TEACHING ASSISTANT JUL-NOV’15
 Basic Electronics Laboratory for B. Tech 1st year students.
 EE360 Embedded systems Laboratory for B.Tech 3rd year students
EXTRA CURRICULARS
 Attended national level workshop “RoboOpus-2012” conducted by Robo Sapians pvt ltd in
association with IIT Delhi.
 Participated in “Recent Trends in electronics and Computation” workshop conducted at IIT
Guwahati.
 Volunteered to work as a webcast engineer in the Assembly Bye- Elections 2012 to Nellore
Constituency, Andhra Pradesh.
 Participated in the Games & Sports and Cultural Activities -2009 held in our university, RGUKT
Nuzvid and secured First prize in cricket.
OTHERS
 Secured 98.2 percentile in GATE 2014.
(References available on request)