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- 1. Power Topologies Review Steve Mappus FAE Training May 2015
- 2. 2 Agenda Non Isolated Converter Topologies and Their Isolated DC/DC Derivatives • PFC Boost • Buck • Buck-Boost Single Ended Converter Topologies • Transformer Reset Techniques • Forward Converter • Flyback Converter Double Ended Converter Topologies • Push Pull • Half Bridge • Full Bridge • Phase Shifted Full Bridge Synchronous Rectification • Current Doubler Rectifier
- 3. 3 DOUBLE-ENDEDSINGLE-ENDED ACTIVE CLAMP 2-SWITCH PUSH-PULL HALF BRIDGE FULL BRIDGE LOW POWER (<100W) MID-POWER (100W-500W) HIGH-POWER (>500W) HARD SWITCHED ZVT/PHASE SHIFT NON-ISOLATED ISOLATED D V V i O = DV V i O − = 1 1 FORWARD D D V V i O − −= 1 SINGLE-ENDED FLYBACK BOOST BUCK-BOOST BUCK ACTIVE CLAMP 2-SWITCH LLC Isolated Power Topology Derivatives 8 “Mainstream” Topologies Non-Isolated 1. Boost 2. Buck-Boost 3. Buck Isolated 4. Flyback 5. Forward 6. Push-Pull 7. Half Bridge 8. Full Bridge
- 4. 4 Other Topologies? Numerous Variations Exist • Sepic • Cuk • Current Fed Buck • Tapped Inductors • Multiple Outputs • Interleaving • More? Different Ways to Operate Them • Voltage Mode Control • Current Mode Control • Digital Control • Variable Frequency • CCM, DCM, BCM • ZVS • ZCS • Synchronous Rectification Some Practical Converter Topology Advice • Most power conversion requirements can be met using one or more of the 8 mainstream topologies • Save more difficult topologies for unique application requirements • Beware of publications proclaiming the “best” topology
- 5. 5 AC Line 85V<VAC<265V VDC=400V 400V to 48V Bus Converter VPOL_1<5V VPOL_N<5V 48V to 12V IBC (Intermediate Bus Converter) Telecom Rectifier Multi-Stage Topology Typical Distributed Power System High Power DC/DCPFC Boost POLDCDCPFCSYS ηηηηη ×××= %9.84%96%95%95%98 =×××=SYSη Scalable, efficient, complex protection functions, sequencing, redundancy, digital control, etc Efficiency example: POL DC/DC
- 6. Non-Isolated Converter Topologies Single Ended Converter Topologies Double Ended Converter Topologies Synchronous Rectification
- 7. 7 Boost Converter Most popular topology for Power Factor Correction • Simple power stage • Efficient energy storage • Continuous input current waveform • VIN<VOUT Operating modes • CCM – fixed frequency, best PF and THD, Any Power Level • BCM – variable frequency, good PF and THD, <300W • DCM – never used intentionally but unavoidable at light load Usually power factor correction capability is lost AC LINE VB EMI Filter DC/DC VLOAD
- 8. 8 Boost Converter VGS(Q) VDS(Q) IL IDS(Q) ID VOUT BCM tON tOFF TS 𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡) × (𝑡𝑡𝑂𝑂𝑂𝑂 + 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 ) = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡) × 𝑇𝑇𝑆𝑆 = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡) = 𝑇𝑇𝑆𝑆 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 = 1 1 − 𝐷𝐷 Inductor volt-second balance: Boost transfer function: VIN<VOUT Most efficient at lower D Continuous input current High PF, low THD CCM, BCM, DCM modes VOUT VAC VIN(t) D IL L VL Q COUTCBYP VOUT VAC VIN(t) D IL L VL Q COUTCBYP 〈𝑉𝑉𝐿𝐿〉 𝑇𝑇 𝑆𝑆 = 𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡) × 𝑡𝑡𝑂𝑂𝑁𝑁 + ��𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡) − 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 � × 𝑡𝑡𝑂𝑂𝐹𝐹𝐹𝐹 � = 0
- 9. 9 Operating Mode 0V VDS tREStOFFtON TS 0A IL 0V VGS VIN VOUT 2x(VIN – VOUT) t IL(PK) 0V VDS tDtOFFtON TS 0A IL 0V VGS t IL(PK) VOUT VAC VIN(t) DIL L Q COUTCBYP TS 0V VDS tOFFtON 0A IL 0V VGS VOUT t IL(PK) IL(MIN) CCM BCM DCM
- 10. 10 Continuous Conduction Mode (CCM) PFC IL Advantages • Low Ripple current: Lower core losses • Lower EMI : Smaller Input Filter • Simple inductor design • Fixed frequency operation, best PF and THD • Can be used at any power level • Easily interleaved for power levels up to many KW Disadvantages Requires very fast boost diode with low IRR Silicon Carbide diodes are often used Larger Inductor MOSFET Switching Loss (hard switching) (1-D)TsDTs Ts IL IDIsw (Not to scale)
- 11. 11 Boundary Conduction Mode (BCM) PFC IL DTs Ts IDIsw Advantages • MOSFET turns on at zero current • ZVS/valley switching • No reverse recovery in boost diode (low cost, low VF diode can be used) • Higher efficiency compared to CCM Disadvantages • Larger MOSFET conduction loss • Variable Frequency • Inductor design can be complex • High peak current limits practical use to ~300W (Impact on EMI filter) (Not to scale)
- 12. 12 Buck Converter VGS(Q) VD VDS(Q) IL IDS(Q) ID VIN VF VL -VOUT VIN-VOUT VIN+VF BCM tON tOFF TS Inductor volt-second balance: Buck transfer function: VIN>VOUT Most efficient at higher D VOUT D VOUT D IL Q L VL L VL Q COUT COUT VIN CIN VIN CIN 〈𝑉𝑉𝐿𝐿〉 𝑇𝑇 𝑆𝑆 = [( 𝑉𝑉𝐼𝐼𝐼𝐼 − 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 ) × 𝑡𝑡𝑂𝑂𝑂𝑂 ] − 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 = 0 𝑉𝑉𝐼𝐼𝐼𝐼 × 𝑡𝑡𝑂𝑂𝑂𝑂 = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × (𝑡𝑡𝑂𝑂𝑂𝑂 + 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 ) 𝑉𝑉𝐼𝐼𝐼𝐼 × 𝑡𝑡𝑂𝑂𝑂𝑂 = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑇𝑇𝑆𝑆 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 𝑉𝑉𝐼𝐼𝐼𝐼 = 𝑡𝑡𝑂𝑂𝑂𝑂 𝑇𝑇𝑆𝑆 = 𝐷𝐷
- 13. 13 Buck-Boost Converter Inductor volt-second balance: Buck-Boost transfer function: VIN<VOUT or VIN>VOUT Used for negative VOUT 〈𝑉𝑉𝐿𝐿〉 𝑇𝑇 𝑆𝑆 = 𝑉𝑉𝐼𝐼𝐼𝐼 × 𝑡𝑡𝑂𝑂𝑂𝑂 + 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 = 0 𝑉𝑉𝐼𝐼𝐼𝐼 × 𝑡𝑡𝑂𝑂𝑂𝑂 = −(𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 ) 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 𝑉𝑉𝐼𝐼𝐼𝐼 = − � 𝑡𝑡𝑂𝑂𝑂𝑂 /𝑇𝑇𝑆𝑆 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 /𝑇𝑇𝑆𝑆 � = − � 𝑡𝑡𝑂𝑂𝑂𝑂 /𝑇𝑇𝑆𝑆 (𝑇𝑇𝑆𝑆 − 𝑡𝑡𝑂𝑂𝑂𝑂 )/𝑇𝑇𝑆𝑆 � 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 𝑉𝑉𝐼𝐼𝐼𝐼 = − � 𝐷𝐷 1 − 𝐷𝐷 � VGS(Q) VD VDS(Q) IL IDS(Q) ID VF VL VIN VIN+|-VOUT| tON tOFF TS VIN+|-VOUT| VOUT-VF -VOUT IL L VL Q COUT D -VOUT VIN IL L VL Q COUT CIN D VIN CIN
- 14. Non-Isolated Converter Topologies Single Ended Converter Topologies Double Ended Converter Topologies Synchronous Rectification
- 15. 15 Benefits of a Transformer AC AC DC Output Load (or DC) D1 L CO Q1 CIN VOVIN D1 D2 L CO NP NS CIN Q1 VIN VO 1. Provides primary to secondary safety isolation – subject to regulatory standards 2. Voltage conversion resolution D V V IN O = D N N V V P S IN O = Ex: For FSW=300kHz (TSW=3.33µs), NP:NS=4:1, 36V<VIN<75 and VO=5V Buck Converter Isolated Buck (Forward) Converter 27%<D<55% 900ns<tON<1.8µs 6%<D<14% 200ns<tON<467ns 3. Multiple outputs can be regulated/quasi-regulated
- 16. 16 Transformer Characteristics NP NS VIN VOUT RP RS LP(LEAK) LS(LEAK) CP(W) CS(W) NP NS LMAGRCORE CP-S(MUTUAL) NP NS VIN VOUT VGS VDS Parasitic Transformer Model CCM Flyback Overshoot/ringing due to Leakage Inductance Ideal transformer • Perfect coupling between Np:Ns • No energy storage Flyback “transformer” • Really a coupled inductor • Primary energy stored during tON • Power transferred during tOFF
- 17. 17 Single Ended Topologies Defined ∝B Vt ∝H NI ∆B B1 B2 +BSAT -BSAT D1 D2 L CO NP NS CIN Q1 Reset Circuit TS +VIN(max) +VIN(min) D=25% D=50% D>50% -VRESET -VRESET OFFRESETONIN tVtV ×−=×+ (max) RESETIN VV −=+ (max) OFFON tt = tON tOFF OFFON tt > INQDS VV ×= 2)1( INQDS VV ×> 2)1( +VIN -VRESET -VIN t t t 0 0 0 OFFRESETONIN tVtV ×−=×+ RESETIN VV −<+ (b) Forward Converter Single Ended – Transformer operation limited to first quadrant (c) Transformer Volt-Second Balance (a) Transformer Hysteresis
- 18. 18 Single Ended Topologies Defined ∝B Vt ∝H NI ∆B B1 B2 +BSAT -BSAT D1 D2 L CO NP NS CIN Q1 Reset Circuit (b) Forward Converter Single Ended – Transformer operation limited to first quadrant (a) Transformer Hysteresis (c) Gapped Flyback “Transformer” D CO NP NS CIN Q1 VIN VO (d) Flyback Converter ∝B Vt ∝H NI ∆B B1 B2 +BSAT -BSAT UNGAPPED GAPPED
- 19. 19 Single Ended Transformer Reset Techniques Reset Winding + Reset Energy Recycled + Simple Off-Line Solution - 50% Duty Cycle Limit (1:1) - Possible Core Saturation - Transformer Structure - Q1 Hard Switched Resonant Reset + Reset Energy Recycled + Fewest Components + Simple Telecom Solution - Repeatable Design Difficult - High VDS Stress - Not for Off-Line Power - Not Suitable for Self-Driven SR - Q1 Hard Switched RCD Reset + Inexpensive Off-Line Solution + >50% Duty cycle Possible - Reset Energy Dissipated - Q1 Hard Switched Active Clamp Reset + High Efficiency (ZVT) + Higher Frequency Operation + Lowest Vds Stress + Off-Line and Telecom + SR Gate Drive - Q1, Q2 Gate Drive - Higher Cost - Limited PWM and/or Driver Choices NP NS Q1 Reset Winding 0 VIN -VR NP NS Q1 RCD Reset 0 VIN -VR NP NS Q1 Resonant Reset 0 VIN -VR Q2 CCL NP NS Q1 Active Clamp Reset 0 VIN -VR
- 20. 20 Flyback Converter Derivation -VOUT L Q COUT D VIN CIN -VOUT L Q COUT D VIN CIN 1:1 -VOUT LM Q COUT D VIN CIN 1:1 (a) (b) (c) (d) (e) a) Non-isolated buck-boost b) Coupled inductor buck-boost c) Isolated buck-boost d) Isolated flyback converter e) D can be in return path VOUT LM Q COUT D VIN CIN n:1 VOUT LM Q COUT D VIN CIN n:1
- 21. 21 Flyback Converter Operating Modes Discontinuous Conduction Mode (DCM) • Advantages (DCM): Smaller transformer, trr of output rectifiers is less of an issue since current is zero before reverse voltage appears, single pole characteristic of the power circuit simplifies compensation • Disadvantages (DCM): Peak currents in the switch and diodes are considerably greater, ripple currents in output capacitors are much greater than continuous mode Continuous Conduction Mode (CCM) • Advantages (CCM) = Peak currents in the switching devices are lower, ripple currents in the output capacitors are lower • Disadvantages (CCM) = Larger transformer is required, right half plane zero (RHPZ) shows up in the control loop thereby complicating compensation Boundary Conduction Mode (BCM) • Variable frequency
- 22. 22 Flyback Converter CCM Operation D D N N V V P S IN O − ×= 1 (a) Flyback Converter (b) CCM Waveforms CCM Transfer Function Limitations • Q1 switching loss (hard switched) • D2 reverse recovery loss • Q1(VDS)>VIN • 50% duty cycle limit • Right half plane zero in CCM VOUT LM Q COUT D VIN CIN n:1 NSNP 0 0 0 0 0 0 PWM VDS VS IQ1 ID1 IL VOUT -(NS/NP)VIN VIN+(NP/NS)VOUT
- 23. 23 Quasi-Resonant Flyback Conventional Valley Switching Wide frequency variation depends on output load condition t t iD vDS T2 Output Power [W] fS[Hz] vDS iD t t T1 Output load decreases Operating frequency increases SOSSLossSwitching fVCP DS 2 ∝
- 24. 24 Quasi-Resonant Flyback Window Valley Switching Ts max =10.8us tB=7.8us tW=3.0us fs_A=110kHz fs_B=122kHz fs_C=127.5kHz fs_D=92.6kHz (a) (b) (c) (d) vDS (100V/div) iD (100mA/div) Time scale 2usec/div Frequency variation depends on output load conditions Operating frequency is within narrow variation (127.5 kHz ~ 92.6 kHz) Light Load Heavy Load
- 25. 25 Two-Switch, Quasi-Resonant Flyback CC CVFB FAN6300H 1 2 3 4 5 6 7 8 NC HV VDD GATEGND CS FB DET FAN7382 1 2 3 4 5 6 7 8 HO VB VS LOCOM LIN HIN VCCPBIAS VIN R1 R2 R3 Q1 Q2 D1 D2 D3 D4D5 ACIN R4 C1 VA VLED VHS C2 C3 (FROM PFC) (FROM PFC) RDY PBIAS
- 26. 26 Two-Switch, Quasi-Resonant Flyback Switching Waveforms 0V VDS 0A IDS tftOFF tON TS 0A ID VAVA 0V 0V VDET 0V VIN PBIAS VIN+VHS VGS(HS) VGS(LS) 0.7V 5µs 2.5V VO OVP IDET(SOURCE)>30µA tDELAY=200ns VRO 2 VRO 2 VIN 2 VIN 2 Quasi-resonant, variable frequency HS and LS MOSFETs switch synchronously Switching period, TS=tOFF+tf+tON Inductor current switches from 0A (ZCS) every switching cycle VDS • ZVS→VOUT>2×VIN • Valley switching→otherwise • Window valley switching
- 27. 27 Two-Switch, Quasi-Resonant Flyback Measured Waveforms Extended Window Valley Switching VOUT< ½ VIN D=11% FS=68kHz POUT=24W VDS Valley Switching on First Valley • VOUT< ½ VIN • D=42% • FS=63kHz • POUT=85W
- 28. 28 Buck Derived Transfer Functions D1 L CO VOVIN D1 L CO VOVIN NP : NS tON tOFF TS D N N V V P S IN O ×= (a) Buck Converter (b) Forward Converter (isolated buck) S ON OFFON ON T t tt t D = + =Duty Cycle = INO VDV ×= ( ) OFFOONOIN tVtVV ×=×− D V V IN O = Buck Converter Transfer Function Forward Converter Transfer Function D N N V V P S IN O ×= All Isolated Single Ended Buck Converters All Isolated Double Ended Buck Converters D N N V V P S IN O ××= 2
- 29. 29 Forward Converter Basics 0 0 0 PWM VDS(Q1) VP VR+VIN VIN IMAG 0 IQ1 IL ID1 ID2 0 0 0 0 VIN R P INR N N VV ×−= D1 D2 L CO NP NSCIN Q1 VIN VO NR D3 (a) Forward Converter with Reset Winding (b) DCM Waveforms (D<0.5) Really a transformer coupled buck Transfer function Limitations • Q1 switching loss (hard switched) • D2 conduction loss • Q1(VDS)>2VIN • 50% duty cycle limit (NP:NR = 1:1) D N N V V P S IN O ×=
- 30. 30 VIN 0 VP IMAG TS DTS D2TS D3TS t t R P IN N N V ×− Why 50% Duty Cycle Limit? (a) Forward Converter: Transformer Voltage and Current 1. Average primary voltage must be zero over switching period 2. Solve (1) for D2 0)0()( 32 =+ −+=〉〈 D N N VDVDV R P ININp 132 =++ DDD 3. By definition (1) (2) (3) 4. Solve (3) for D3 01 23 ≥−−= DDD (4) P R N N DD =2 5. Sub (2) into (4) 01 ≥−− P R N N DD (5) 6. Solve (5) for D (6) P R N N D + ≤ 1 1 7. For NP:NR=1:1 (common practice) (7) 2 1 ≤D
- 31. 31 Problems with Duty Cycle > 50% VIN 0 VP IMAG TS DTS D2TS D3TS t t R P IN N N V ×− Equal Vxt Area VIN VP IMAG t t R P IN N N V ×− 2TS 3TSTS DTS D2TS D=67% D=40% Unequal Vxt Area Common practice is to use 1:1 bifilar transformer winding for NP:NR D=40% • Converter operates in DCM • Transformer is completely reset on every switching cycle D=67% • Converter wants to operate in CCM • Transformer can NOT reset on every switching cycle • IMAG increases due to volt second product imbalance • Transformer saturation will result • Operation beyond D=50% requires additional reset voltage
- 32. 32 Duty Cycle Greater Than 50% VDS vs Vin Third Winding Reset 72 84 96 108 120 132 144 156 168 180 192 204 216 36 42 48 54 60 66 72 Vin (V) VDS(V) Np:NR=1:1 Np:NR=1:2 NP NS Q1 NR VDS VIN VP IMAG t t R P IN N N V ×− 2TS 3TSTS DTS D2TS D=67% Equal Vxt Area } } NP:NR=1:1 NP:NR=1:2 For NP:NR=1:2 VDS=3VIN Conclusion: Reset winding technique, D>50% not practical for high VIN applications due to additional MOSFET VDS stress
- 33. 33 Active Clamp Forward Converter D1 D2 L CO NP NS CIN Q1 Q2 CCL 0 0 0 0 PWM Q1 VDS VP IQ1 VIN VRESET VIN+VCL 0 Q2 VGS IMAG ICL 0 IP Advantages • Reduced MOSFET VDS voltage stress • Higher efficiency through ZVS • Use of parasitic elements • Higher frequency operation • Square wave transformer reset for SR applications • Suitable for off-line (HS clamp) or DC/DC (LS clamp) Disadvantages • Conditional ZVS only • Dual primary side gate drive with accurate dead-time control and max duty cycle clamp required • Poor transient response due to CCL Transfer Function D N N V V P S IN O ×=
- 34. 34 Active Clamp Forward Converter Two Versions D1 D2 L CO NP NS CIN Q1 Q2 CCL D1 D2 L CO NP NS CIN Q1 Q2 CCL (a) High-Side Active Clamp (Flyback Clamp) (b) Low-Side Active Clamp (Boost Clamp) INV D × −1 1 INV D × −1 1 INV D D × −1 INV D D × −1 INV D D × −1 INV D × −1 1 PARAMETER HIGH-SIDE ACTIVE CLAMP (off-line) LOW-SIDE ACTIVE CLAMP (telecom) VDS VRESET VCL CCL (applied voltage) Lower voltage by VIN volts Highest VCL occurs at DMAX Higher voltage by VIN volts Not practical for off-line CCL (cap value) Same value as low-side for given ripple voltage Same value as high-side for given ripple voltage Clamp MOSFET (Q2) N-Channel Can be used for >500V P-Channel Can be used up to 500V Gate Drive Gate drive transformer required Level shifting gate drive required
- 35. 35 Active Clamp Forward Converter VDS Voltage Stress VDS vs Vin Active Clamp Reset 75 85 95 105 115 125 135 145 36 42 48 54 60 66 72 Vin (V) VDS(V) N=5 N=6 N=7 SECIN IN INDS VNV V D VV ×− = − ×= 2 1 1 Telecom Converter Example VVV IN 7236 ≤≤ S P N N N =, where VVO 3.3= Optimize transformer turns ratio, N, to minimize VDS voltage stress over entire VIN range For N=6 • VDS=108V at VIN(MIN) and VIN(MAX) • VDS≤1.5VIN at VIN(MAX) N=5 N=6 N=7 DMIN=28%DMAX=55% IN O V NV D × = IMPORTANT – Accurate max duty cycle clamp or volt-second clamp is necessary due to the parabolic nature of VDS near DMAX
- 36. 36 Active Clamp Forward Converter Clamp Capacitor D1 D2 L CO NP NS CIN Q1 Q2 CCL 0 0 PWM Q1 VDS VIN+VCL 0 Q2 VGS VCL(Ripple) = 0% VCL(Ripple) = 50% Clamp capacitor optimal • VCL(RIPPLE) = 10%-20% VCL(Ripple) = 10% Q1 VDS Waveforms verses Clamp Capacitor Value: Clamp capacitor too small • VCL(RIPPLE) = 50% • Better transient response • Increase VDS stress Clamp capacitor too large • VCL(RIPPLE) = 0% • Lowest VDS stress • Poor transient response Choosing Clamp Capacitor • Capacitor needs to be large enough to approximate the clamp voltage as DC • Initially calculate CCL according to “Rule of Thumb” • Select CCL voltage rating according to maximum clamp voltage PLUS allowable ripple voltage and safety margin )(2 MAXoffCLMAG tCL >××π ( ) 2 2 )2( 1 10 swMAG MIN CL FL D C ×× − ×> π
- 37. 37 Active Clamp Forward Converter Zero Voltage Switching (ZVS) ZVS occurs when the voltage across the MOSFET, VDS, is positioned to “zero volts” prior to the start of the next switching cycle. Benefits of ZVS • Reduced switching losses • Higher operating frequency possible (smaller passive component size) • Higher converter efficiency • Increased reliability • Reduced radiated emissions (EMI) VDS ID PSW=VDS x ID x FSW (a) Hard Switching (b) “Ideal” ZVS
- 38. 38 Active Clamp Forward Converter Zero Voltage Switching (ZVS) D1 D2 L CO Q1 Q2 CCL D2 CDS D1 CDS VDS RP RS LP(LEAK) LS(LEAK) CP(W) CS(W) NP NS LMAGRCORE CP-S(MUTUAL) CD1 CD2 Parasitic elements can be used to benefit ZVS Active Clamp Forward converter uses fixed frequency resonant transitions to achieve ZVS when specific operating conditions are met
- 39. 39 Active Clamp Forward Converter Zero Voltage Switching, Q1 Turn-Off IM + IO N IC VIN VDS 0 VIN VDS IM IO N VGS(Q1) VGS(Q2) ZVS turn-off is easy • Magnetizing current, IM +, and reflected secondary current combine to fully charge the resonant capacitance, C ( )2 2 2 1 2 1 CLINDSM O M VVCI N I L +> + + NOTE: leakage inductance is neglected for this analysis D1 D2 L CO NP NS CIN Q1 Q2 CCL
- 40. 40 Active Clamp Forward Converter Zero Voltage Switching, Q1 Turn-On IM - IO N IC VIN VDS , for ZVS turn-on − MI 0 VIN VDS IM IO N VGS(Q1) VGS(Q2) N I I O M >− VDS VGS(Q1) 1 - Non-ZVS 2 - Optimal ZVS 3 - ZVS (2, 3) - ZVS 1 - Non-ZVS (Miller) ZVS turn-on is difficult • Magnitude of IM - must be greater than the magnitude of the reflected secondary current during entire ZVS window • Must be enough resonant current to fully discharge C • Must be enough dead time for the drain voltage to fully resonate to near zero volts N I I O M >− ( )2 2 2 1 2 1 CLINDSM O M VVCI N I L +> − − DSMRES CLt ×≥ 2 π NOTE: leakage inductance is neglected for this analysis
- 41. 41 Single Ended (<500W) 2 Switch Forward Converter D1 D2 L CO NP NSCIN Q1 Q2 D3D4 0 0 0 PWM (Q1, Q2) VDS (Q1, Q2) VS VIN/NP VIN VIN/2 ID3, ID4 -VIN/NP 0 IQ1, IQ2 0 IL ID1 ID2 0 0 IO IMAG0 Advantages Ruggedness MOSFET voltage stress limited to VIN Magnetizing energy recycled by D3, D4 Universal input, 150W<P<500W Disadvantages Limited to less than 50% duty cycle High side gate drive required for Q2 Hard switching Transfer Function D N N V V P S IN O ×=
- 42. 42 Single Ended (>1kW) Interleaved 2 Switch Forward Converter D1 D2 L CO NP NSCIN Q1 Q2 D3D4 D5 D6 L NP NS Q3 Q4 D7D8 Dn Dn L NP NS Qn Qn DnDn Advantages • Can operate multiple power stages out of phase • Ripple current cancellation at output capacitor • Reduced RMS current at input capacitor • Multiple stages can add up to kW of power • Smaller output inductors can improve transient response Disadvantages • Design complexity • PCB layout can be challenging
- 43. Non-Isolated Converter Topologies Single Ended Converter Topologies Double Ended Converter Topologies Synchronous Rectification
- 44. 44 Double Ended Topologies Defined ∝B Vt +BSAT ∝H NI -BSAT ∆B B1 B2 ∝B Vt ∝H NI ∆B B1 B2 +BSAT -BSAT ∆B B1 B2 (RCD Reset) (Active Clamp) Normal Flux Imbalance Saturation Primary Current Double Ended – Transformer operation occurs in first and third quadrants Active Clamp Forward “Single ended” but operates slightly into the third quadrant Half-Bridge, Full-Bridge Symmetrical operation between first and third quadrants No transformer reset circuitry required
- 45. 45 Double Ended (<500W) Push Pull Converter D1 D2 L CO NP NS Q1 NS Q2 CIN NP PWM, Q1 PWM, Q2 IQ1 IQ2 VDS(Q1) 2VIN VDS(Q2) 2VIN ID1 ID2 ILIO Advantages • Lower primary current compared to HB • Best for lower VIN, such as telecom DC/DC of US Line Voltage • Simple low-side gate drive Disadvantages • High voltage (2xVIN) on primary MOSFETs • Transformer flux walking (VMC only) • Center tapped transformer structure • Hard switching Transfer Function D N N V V P S IN O ××= 2
- 46. 46 Double Ended (<500W) Half Bridge Converter (Symmetrical) D1 D2 L CO NP NS Q1 NS Q2 CIN C1 C2 VP VDS(Q1, Q3) VIN VDS(Q2, Q4) VIN ID1 ID2 IL IO VP IP VIN/2 PWM, Q1 PWM, Q2 -VIN/2 Advantages • Better transformer utilization • MOSFET voltage stress limited to VIN • Best for high VIN off line applications up to 500W • Single winding primary • Transformer balanced by C1 and C2 • Asymmetric and resonant versions can ZVS Disadvantages • Totem pole primary gate drive • High primary current • Possible cross conduction between Q1 and Q2 • Hard switching Transfer Function D N N V V P S IN O ××= 2
- 47. 47 Asymmetrical Half Bridge Converter + Vp - + Vd - + Vp - 1 : 1 0 Asymmetric square waveform Symmetric square waveform Vd Vd 0 CB + Vp - + Vd - + VCB - Same area VCB + Vp - 1 : 1 0 0 What if an asymmetric square wave were introduced to the transformer? Transformer will be saturated What if an asymmetric square wave were introduced to the transformer in series with a DC blocking capacitor? Not saturated due to the voltage of the blocking capacitor, CB
- 48. 48 Asymmetrical Half Bridge Converter VP IP Q2 (D) Q1 (D) VIN/2 -VIN/2 D=0.46 D=0.23 VIN/2 -VIN/2 VP IP Q2 (D) Q1 (1-D) VIN-VCB VCB VCB D=0.46 D=0.23 Equal Area VIN-VCB (a) Symmetrical HB waveforms (b) Asymmetrical HB waveforms Asymmetrical Gate Drive • Q2 modulated by D • Q1 driven by 1-D • Fixed dead time between Q1 and Q2 • Dead time optimized for ZVS and anti cross conduction • Fixed frequency ZVS PWM operation • Near D=0.5, operation is same as symmetrical HB BUT, excessive voltage stress is applied to secondary rectifier at VIN(MAX) ( )DD N N V V P S IN O −×××= 12 D1 D2 L CO NP NS Q1 NS Q2 CIN CB VP
- 49. 49 Asymmetrical Half Bridge VD vs D 50 75 100 125 150 175 200 225 250 0.20 0.23 0.26 0.29 0.32 0.35 0.38 0.41 0.44 0.47 0.50 Duty Cycle DiodeVoltageStress(V) VD1 VD2 Asymmetrical Half Bridge Converter Secondary Rectifier Voltage Stress Reverse recovery and parasitic ringing Wide DD Range requires use of high voltage rectifiers Converter operates best at D=0.5 D V V O D − = 1 1 OD VDV ×=2
- 50. 50 Asymmetrical Half Bridge Converter Advantages • Fixed frequency ZVS • Constant power transfer (D and 1-D) reduces output ripple • Power stage can be controlled using any active clamp PWM controller Disadvantages • High voltage stress on secondary rectifier • Loss of ZVS at some min load current – extending ZVS range is difficult • Poor transient response due to blocking capacitor, CB
- 51. 51 LLC Resonant Half Bridge Converter Square wave generator: produces a square wave voltage, Vd by driving switches, Q1 and Q2 with alternating 50% duty cycle for each switch. Resonant network: consists of Llkp, Llks, Lm and Cr. The current lags the voltage applied to the resonant network which allows the MOSFET’s to be turned on with zero voltage. Rectifier network: produces DC voltage by rectifying AC current Ip Ids2 Vd (Vds2) Vgs2 Im Vin ID Vgs1 + VO - Ro Q1 Q2 n:1 Ip Llkp Lm Cr Ids2 Vd Llks Im ID Vin Square wave generator resonant network Rectifier network Io
- 52. 52 LLC Topology Variations VIN Lr Lm Cr Q1 Q2 VIN Lr Lm Cr Q1 Q2 VIN Lr Lm ½ Cr Q1 Q2 ½ Cr VIN Lr Lm ½ Cr Q1 Q2 ½ Cr + VO - Ro + VO - Ro + VO - Ro + VO - Ro Primary Side Variation Secondary Side Variation Transformer across the high side MOSFET Transformer across the low side MOSFET Split resonant capacitor with clamping diode Split resonant capacitor Full bridge rectifier with single winding 2 Rectifier diode with center tab winding Voltage doubler rectifier with single winding Synchronous rectifier with center tab winding
- 53. 53 LLC Resonant Half Bridge Converter Advantages of the LLC resonant converter • Narrow frequency variation range over wide load range • Zero voltage switching even at no load condition • Reduced switching loss through ZVS Improved efficiency and EMI • When the two magnetic components are implemented with a single core (use the leakage inductance as the resonant inductor), one component can be saved
- 54. 54 LLC Resonant Half Bridge Converter Disadvantages of the LLC resonant converter • Can optimize performance at one operating point, but not with wide range of input voltage and load variations (too wide frequency range) • Difficult to regulate the output at no load condition • Significant current may circulate through the resonant network, even at the no load condition • Quasi-sinusoidal waveforms exhibit higher peak values than equivalent rectangular waveforms • High output current ripple
- 55. 55 Double Ended (<500W) Push Pull Converter D1 D2 L CO NP NS Q1 NS Q2 CIN NP PWM, Q1 PWM, Q2 IQ1 IQ2 VDS(Q1) 2VIN VDS(Q2) 2VIN ID1 ID2 ILIO Advantages • Lower primary current compared to HB • Best for lower VIN, such as telecom DC/DC of US Line Voltage • Simple low-side gate drive Disadvantages • High voltage (2xVIN) on primary MOSFETs • Transformer flux walking (VMC only) • Center tapped transformer structure • Hard switching Transfer Function D N N V V P S IN O ××= 2
- 56. 56 Double Ended (>500W) Full Bridge Converter (PWM) D1 D2 L CO NP NS Q3 NS Q4 CIN Q1 Q2 Gate, Q1 Gate, Q2 VDS(Q1, Q4) VIN VDS(Q2, Q3) VIN ID1 ID2 IL IO Gate, Q3 Gate, Q4 VP IP VIN -VIN Advantages • MOSFET voltage stress limited to VIN • Twice the power compared to half bridge • Single winding primary Disadvantages • Dual, totem pole primary gate drive • Hard switching (Non-ZVT) • Parasitics degrade circuit performance • Circuit complexity Transfer Function D N N V V P S IN O ××= 2
- 57. 57 Double Ended (>500W) Phase Shifted Full Bridge Converter D1 D2 L CO NP NS Q3 NS Q4 CIN Q1 Q2 Gate, Q1 Gate, Q2 VDS(Q2, Q3) VDS(Q1, Q4) ID1 ID2 IL IO Gate, Q3 Gate, Q4 VP IP VIN -VIN VIN Freewheel Power Freewheel Power VIN Advantages • High Efficiency ZVS • Highest single stage processing power • MOSFET voltage stress limited to VIN • Twice the power compared to half bridge • Full wave rectified secondary • Excellent choice for EU line voltage (PFC pre- regulator) with output power >1kW Disadvantages • Dual, high side primary gate drive • Circuit complexity • High circulating primary current for ZVS • Loss of ZVS at light load current Transfer Function D N N V V P S IN O ××= 2
- 58. 58 Phase Shifted Full Bridge Converter ZVS Waveforms (a) IO=100% (b) IO=35% (c) IO=0% Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q2 P→A Q4 A→P VDS VGS VDS VGS A=Active (Power) P=Passive (Freewheel)
- 59. 59 Phase Shift Control vs ZVT PWM Control A B C D VPRI IPRI UL(A) LL(B) UR(C) LR(D) VPRI IPRI UR(C) LR(D) UL(A) LL(B) ZVT PWM Control • Upper bridge FETs are fixed at 50% D • Lower bridge FETs are trailing edge PWM • Resonant delay set on lower FET leading edge Freewheel period • Both SRs are ON • Reduces reflected secondary current since current only flows through both SRs • Less available ZVS current Phase Shift Control • All bridge FETs are fixed at 50% D • A and B are synced to clock • C and D are phase shift modulated • Resonant delay set between AB and CD Freewheel period • Secondary-side load current freewheels through transformer and is reflected to primary • Reflected current aids ZVS • Higher conduction losses at higher power
- 60. 60 Phase Shift Control vs ZVT PWM Control ZVT PWM Control • Current freewheels through one high-side active FET and body-diode of other high-side FET during each FW period Phase Shift Control • Current freewheels through two active high-side FETs for first FW period then through two active low-side FETs for second FW period Freewheel ResonantFreewheel Resonant ( )ONDSFWDISS RIP _ 2 2 ××= ( )ONDSFWFWFSWBDDISS RIIVFtP _ 2 ×+×××=
- 61. 61 ZVT PWM Control Upper Bridge MOSFET Body-Diode Conduction Freewheel (FW) Period • For 36V<VIN<72V • Body-diode conduction is 970ns at VIN=72V Minimize body-diode conduction in upper MOSFETs • Pre-regulate input voltage (PFC) Still have to deal with brown-out and hold-up • Operate converter at lowest frequency possible VVF 1= AI FW 2= nstBD 970= kHzFSW 265= Ω= mR ONDS 25_ mWVAkHznsPBD 51412265970 =×××= mWmAP ONRDS 100252 2 )( =Ω×= Measured Values Calculated Body-Diode Conduction Loss in each Upper FET Calculated Channel Conduction Loss in each Upper FET Total Conduction Loss for each FW period (ZVT PWM Control) Total Conduction Loss for each FW period (PSFB Control) Comparison of FW MOSFET Conduction Losses for Telecom DC/DC App VVIN 72= AIOUT 10= *Assume switching, gate charge, Coss losses are same for each control method mWmWmWP ZVTPWMFW 614100514)(1 =+= mWmWmWP ZVTPWMFW 614100514)(2 =+= mWmWP PSFBFW 2001002)(1 =×= mWmWP PSFBFW 2001002)(2 =×= (25%) (UL and UR) (UL and UR) (A and B) (C and D)
- 62. 62 High Power Topology Summary D1 1 VIN − × Topology Transformer Primary Switches VDS “Ideal” Application CCM Boost Inductor (non-isolated) 1 VOUT High power PFC >300W Interleaved PFC >Several kW BCM Boost Inductor (non-isolated) 1 VOUT PFC <300W Interleaved PFC <1kW Forward Single-end 1 2xVIN <200W, universal off-line or telecom Active Clamp Single-end 2 <500W, universal off-line or telecom, highest efficiency required 2-Switch Forward Single-end 2 VIN <500W, universal off-line, PFC pre-regulator Half Bridge Double-end 2 VIN <500W, EU off-line, Intermediate Bus Converters Push Pull Double-end 2 2xVIN <500W, telecom or low VIN (<200V) Full Bridge Double-end 4 VIN >500W, universal off-line Phase Shifted FB Double-end 4 VIN >1kW, universal off-line or telecom, highest efficiency required Current Doubler Double-end NA NA Any double-ended topology, low VOUT, high IOUT most benefit
- 63. 63 LLC vs AHB Comparison LLC resonant converter Asymmetric Half-bridge Control method Variable frequency with fixed duty cycle (50%) PWM with fixed frequency Practically input voltage range Vmax /Vmin =1.2~1.4 Vmax /Vmin =1.2~1.3 Primary side MOSFET voltage Clamped to the input voltage Clamped to the input voltage Secondary side rectifier voltage stress 2 times the output voltage (for center tapped transformer) Usually about 3 to 6 times the output voltage for powering and freewheeling diodes, respectively (for center tapped transformer) Output capacitor current ripple Almost twice the output current (peak-to-peak) Several tens % of output current (peak-to-peak) ZVS condition ZVS is easily achieved from full load to no load condition using the energy in the magnetizing inductance ZVS is difficult to achieve at light load condition ZVS at full load condition is relatively easy Other features No simple power limit capability such as pulse-by- pulse current limit in PWM operation Requires tight tolerance of resonant components (L,C) Relatively large circulating current Tight tolerance is not required for the resonant components (L,C) + VO - Ro Q2 Q1 Vin Io Lr Lm CB + VO - Ro Q1 Q2 Vin Io Lr Lm Cr
- 64. Non-Isolated Converter Topologies Single Ended Converter Topologies Double Ended Converter Topologies Synchronous Rectification
- 65. 65 Synchronous Rectification (SR) D1 D2 L CO NP NS CIN Q1 Reset Circuit Efficiency vs Output Voltage Vf=0.4V, Vf=1V 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.5 1.7 2.8 4.0 5.1 6.3 7.4 8.6 9.7 10.9 12.0 Output Voltage (V) Efficiency Vf=0.4V Vf=1V Q2 Q3 L CO NP NS CIN Q1 Reset Circuit What is Synchronous Rectification? • Replacing secondary side discrete rectifiers (D1, D2) with MOSFETs (Q2, Q3) Benefits of SR • Parallel MOSFETs • Increase efficiency Lower output voltage and higher current applications benefit most How do we drive them? OUT FOUTFOUTOUT OUTOUT IN OUT V VIVIV IV P P + = ×+× × == 1 1 η
- 66. 66 Single Ended Synchronous Rectification SR Gate Drive Options Q3 Q4 L CO NP NS CIN Q1 Q2 CCL Q3 Q4 L CO NP NS CIN Q1 Q2 CCL SR Gate Drive Self-Driven SR SR gate drive derived from transformer (as shown) or output inductor Advantages • Simple – no timing issues • High efficiency for few components Disadvantages • SR gate drive not regulated • Difficult when VIN > 2:1 • No control of secondary during start-up • Not compatible with all reset techniques Control-Driven SR SR gate drive comes from PWM control signal Advantages • SR gate drive is regulated • Can be used for wide VIN applications • Secondary is controlled by primary Disadvantages • Primary to secondary timing
- 67. 67 Q3 Q4 L CO SR Gate Drive Reset Circuit NP NS CIN Q1 D 1-D Single Ended “Hybrid” SR SR Gate Drive Options Hybrid-Driven SR • Combination of control driven and self driven • Forward SR (Q3) self driven by D • Free wheeling SR (Q4) driven by PWM inverted (1-D) Applications • Forward converter operating in DCM • RCD, Resonant and Third Winding Reset
- 68. 68 NP Q3 Q4 CIN Q1 Q2 Q5 L1 CO NS L2 Q6 SR Gate Drive T1 Double Ended Synchronous Rectification (>1kW) (a) Full Bridge with Current Doubler SR Secondary SR applications typically greater than 12V output Highest efficiency • Minimize body-diode conduction • Use Secondary sensing for best timing SR driver solution is strongly related to control scheme • Primary side PWM control Need signal and timing from pri-to-sec for good SR control Difficult to adapt over line/load changes • Secondary side PWM control Allows sensing key nodes for timing optimization Cross boundary with timing to communicate with primary Direct drive between PWM and SR Needs startup bias supply Double ended control driven SR drive is the more difficult SR problem to solve
- 69. 69 Double Ended (All) Current Doubler Rectifier D1 D2 L CO NP NS NS VO D1 D2 L CO NP NS NS VO D1 D2 CO VO V I V D1 D2 CO VO V I I What is it? - A full wave alternative rectification technique compatible with all double ended converter topologies D1 D2 CO VO L2 L1 NP NS NP NS D1 D2 L1 CO L2 VO NP Q1 L1 CO NS L2 Q2 VO OR Current Doubler Derivation of Current Doubler (a) (b) (c) (d) (e) (f) (g)
- 70. 70 Double Ended (All) Current Doubler Rectifier Operation t3 t4 Q3 Q4 CIN Q1 Q2 D1 D2 L1 CO L2 Q3 Q4 CIN Q1 Q2 D1 D2 L1 CO L2 t2 t3 Q3 Q4 CIN Q1 Q2 D1 D2 L1 CO L2 t1 t2 Gate, Q1 Gate, Q2 IO=IL1+IL2 Gate, Q3 Gate, Q4 VP IP IL1 IL2 VL2 VL1 t0 t1 t2 t3 t4 Q3 Q4 CIN Q1 Q2 D1 D2 L1 CO L2 t0 t1 Current Doubler Timing Diagram (PSFB Application) Current doubler benefits: • Better thermal distribution for higher current outputs • Each inductor carries half the load current at half the switching frequency • Ripple currents cancel as a function of D • Single winding secondary
- 71. 71 Choosing the “best” topology: • Is the output voltage higher or lower than the input voltage range? • Are there isolation requirements? • Are multiple outputs required? • AC input – PFC/THD requirements? • Output power? • What is the maximum input/output voltage? • What is the maximum input/output current? Fine tune topology choice by trading off: • Efficiency • Performance • Cost • Size Q&A? Summary
- 72. THANK YOU