2. PSpice Simulation Convergence Guide
• .OPTION setting guide
• PSpice Standard Default
• Simulation Convergence Quick Fix
• Maximum Step Size
• SKIPBP
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3. .OPTION setting guide (1/2)
.OPTIONS Default Suggestion Explanation
RELTOL 0.001 0.01 • Increase simulation speed by 10 to 50%
VNTOL 1u 1m
• Aid convergence but reduce the voltage
accuracy
ABSTOL 1p
1n, 1u or
Increase to 10u
• Aid convergence but reduce the current
accuracy
• Should be 8 order of magnitude below the
level of the maximum current (ABSTOL <
I[MAX]/108)
CHGTOL 0.01p 0.01u
• If capacitor are in order of Farad, increase
CHGTOL by six order of magnitude
GMIN 1E-12 1E-9 ~ 1E-8
• Please note that Vswith model parameter
ROFF is limited by 1/GMIN
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4. .OPTION setting guide (2/2)
.OPTIONS Default Suggestion Explanation
ITL1 150 200, 400, 500
• This increases the number of DC iterations
that PSpice will perform before it gives up.
• In the complex circuit, further increases in
ITL1 (e.g. 1000) won’t aid convergence.
ITL2 20 50, 100, 200
• This increases the number of DC iterations
that PSpice will attempt before it gives up.
ITL4 10 40, 100, or 500
• This increases the number of transient
iterations that PSpice will attempt at each time
point before it gives up.
• Values greater than 100 won’t usually bring
convergence
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7. Maximum Step Size
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• To increase (or decrease in some
cases) the Maximum step size might
help the simulation to complete
– e.g. Increase the Maximum step
size from 10n to 100n can cause
the simulation to complete.
8. SKIPBP
Skipping the bias point
Check the SKIPBP option to skip the bias
point calculation for the transient analysis
Please note that this setting should be used
as a last resort if there is trouble getting the
transient analysis to start because the DC
operating point can’t be calculated.
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