My skills: HDL : Verilog HVDL : System verilog HVL : UVM methodology Scripting language : Perl

1. VARUN DAVE
Mobile: +918511516512, +918147838715
E-Mail: ervarun12.vd@gmail.com
LinkedIn : https://in.linkedin.com/in/varun-dave-04a7b3104
CAREER OBJECTIVE
To pursue a challenging career in the field of Semiconductor with constant contribution to an
organization that provides challenging work environment and the opportunity for professional
growth.
PROFILE SUMMARY
• ASIC Design and Verification Intern at “Maven Silicon”.
• Lecturer at Ipcowala Institute of Engineering and Technology.
• Pursued certification course in VLSI design and verification.
• Bachelor of Engineering in Electronics and Telecommunications [E.T.C.].
SKILLS
Domain ASIC Front‐end Design and Verification
HDL Verilog
HVL System Verilog
TB Methodology UVM(Universal Verification Methodology)
Verification
Methodology
Coverage Driven Verification, Assertion based verification –SVA,
Random-Constraint Verification
EDA Tools Xilinx–ISE, Questasim, Modelsim, Rivera‐PRO
Operating Systems Windows, Linux
Scripting language PERL, TCL
Personal strengths Team Management, Debugger , Quick Learner
EMPLOYMENT DETAILS
● Profile: Verification Intern
Institute : Maven Silicon
Duration: September ’15 – Till the Date
➢ Good understanding of design specification.
➢ Write verification plan through design specification
➢ Architected Reusable Testbench in UVM.
➢ Verified the IPs with system Verilog.
➢ Design the RTL module using Verilog.
➢ Generated Functional, Code and Assertion Coverage.
➢ Good knowledge of the bus protocol and applied in designing and verifying IPs.

2. ● Profile: Lecturer
Institute: Ipcowala Institute of Engineering and Technology Duration: Jan’14 –
August’14
➢ Was responsible for subjects of Microprocessor, Advanced microprocessor and Basic
Electronics.
➢ Able to understand the processor specification and guide to enhance the processor.
EDUCATION
2013: B.E. (E.T.C.) from Birla Vishwakarma Mahavidyalaya, Gujarat Technical University, ‐ CGPA:
6.71
2009: 12th from RPTP Higher Secondary School ‐ Percentage: 78%
2007: 10th from I. B. Patel School ‐ Percentage: 80.6%
PROJECTS
 VIP of Advanced Xtensible Interface (AXI)
Organization Maven Silicon
Description Virtual Intellectual Property (VIP) of Advanced Xtensible
Interface (AXI) is used to create property in IP block of high
performanceto act asamaster orslaveforthe particularother
connected IP and mostly used as in SOC based design.
My Role ● Designed a VIP using UVM
● Verified the scenarios like simple data transfer and by
multiple outstanding.
 AHB - APB Bridge (Design Using Verilog)
Organization Maven Silicon
Description AHB to APB Bridge interfaces between AMBA High
Performance IPs and AMBA Peripheral IPs. It is required to
bridge the communication gap between low bandwidth
peripherals on APB with the high bandwidth ARM
Processors and/or other high‐speed devices onAHB. This is to
ensure that there is no data loss between AHB to APB or APB
to AHB data transfers.
My Role
- Designed RTL using Verilog.
- Verified the design using one initiator (AHB master) and one
target (APB interface) using linear test‐bench using Verilog.

3.  SPI Design Verification (UVM)
Organization Maven Silicon
Description An already designed RTL of SPI core is verified using UVM.
Multiple test cases were implemented for all the functional
modes of SPI.
My Role Create a verification test plan.
Created testbench using UVM.
Implemented multiple testcases in UVM.
 Router Designing and Verification (Verilog and UVM)
Organization Maven Silicon
Description A 1X3 Router (capable of routing the data packets to three
different clients form a single source network) was designed,
including a register module that can hold data packets
momentarily, to pass onto three different FIFO memories
along with a Finite State Machine and a Synchronizer that can
manipulate the internal signals to carryout the necessarytask
in convenient manner.
My Role ● Design a Router of single server and three clients using
Verilog.
● Verified a Router using UVM by creating a configurable
and reusable testbench.
 Digital alarm and temperature sensor using GSM application
Organization Prompt Softech Pvt.Ltd.
Description It senses the temperature and timer and displays to the LCD
and it sends the information to GSM module.
PERSONAL DETAILS
Date of Birth: 12th February, 1992
Address: 223, Sai Vandana Brundavan, Sarjapur Road, Doddakannelli
Marital Status: Married
Languages Known: English, Hindi and Gujarati.