Status of Panel Level Packaging 2018 Report by Yole Developpement

© 2018
From Technologies to Markets
Sample
Panel Level
Packaging
Status 2018
Image source: Powertech Technology Inc

2
Biography & contact
Status of Panel Level Packaging 2018 Report | Sample | www.yole.fr | ©2018
ABOUTTHE AUTHOR
SantoshKumar
Santosh Kumar works as a Senior Technology & Market Research Analyst at Yole Développement, the "More than Moore" market research and
strategy consulting company. He is involved in the market, technology, and strategic analysis of microelectronic assembly and packaging technologies.
He received a Bachelor’s degree and a Master’s degree in Engineering from the Indian Institute of Technology (IIT) Roorkee and the University of
Seoul, respectively. He has published more than 40 papers in peer-reviewed journals and has obtained two patents. He has presented and given talks at
numerous conferences and technical symposia related to advanced microelectronics packaging.
Contact:kumar@yole.fr

3Status of Panel Level Packaging 2018 Report | Sample | www.yole.fr | ©2018
AMS,Amicra Microtechnologies,Amkor, Analog Devices,Apple,Applied Materials,Asahi Kasei,ASE,ASM Pacific,AT&S,Atotech,
AVX, Besi, Bosch,Canon, CEA-LETI, Continental, Dai Nippon, Daimler, DNP, DYCONEX AG, Dow Electronic Materials,Evatec,
EVG Group, Ford, Fujikura, GaN Systems,General Electric, Grand Plastic Technology, Hanmi, HD Micro/DuPont,Heidelberg
Instruments,HighTec EDV System,Huawei,Ibiden, Infineon, Intel, Intevac,IPDiA, IMEA*Star, IMEC, ITRI, IZM Fraunhofer, J-
Devices,JSR Micro, Kulicke & Soffa (K&S), Kyocera,Maxim, Merck/AZ EM,Mitsui Kinzoku, Murata Electronics,Nagase,Nanium,
NCAP China, Nikon, Nitto Denko, ON Semiconductor, Orbotech,ORC, Panasonic, PowertechTechnologies,Qorvo,Qualcomm,
Ramgraber,Rohm Semiconductor, Rudolph, Sarda Technologies,Schweizer, SCREEN, Shinko, Shin Etsu,STMicroelectronics,SUSS
MicroTec,Shin-Etsu MicroSi, Samsung Electro Mechanics (SEMCO),Semsysco, STATS ChipPAC, TaiyoYuden,Tango,Tazmo,TCL,
TDK-EPCOS,TEL,Texas Instruments (TI),Thales,Towa,TransSiP,Tokyo Ohka Kogyo Co., LTD. (TOK), TSMC, Ultratech,Ulvac,
Unimicron, USHIO, UTAC,Valeo,Vishay,Yamada and many more…
COMPANIES CITED INTHIS REPORT

REPORT OBJECTIVES (1/2)
• This technology and market report is update of the Yole 2015 report “Status of Panel Level
Packaging and Manufacturing”
• The reports is updated because there is sustained interest in the industry towards the panel level
packaging to avail potential cost reduction and since 2015, many new developments have taken
place towards this goal. Big players have entered this business that has potential to change the
packaging landscape. Many equipment and material companies have entered this business because of
which the gap in the supply chain in panel level packaging has narrowed down. Industry players are
closely watching the developments in panel level packaging to explore the opportunities and to
position themselves strategically to avail its benefits.
• The objectives of this report are to:
o Provide an overview of the panel packages technologies
o Describe the key applications that could use the panel infrastructure
o Identify the panel packages solutions and players supporting these packages
o Identify the current and future industrial players for each packaging technology based on panel level
o Provide market data and forecasts on panel products
o Determine the competitive landscape for each segment

REPORT OBJECTIVES (2/2)
Additional objectives of this report are to:
o Assess the market for panel manufacturing, providing a forecast for 2017–2023 in terms of revenue and
wafer starts
o Create a roadmap of the players involved
o Analyse packages technologies basedon the Panel Level and trends
o Identify trends in overall equipment & materials for panel processing
o Identify manufacturing challenges related to the panel infrastructure
o Provide an overview of the technological trends for panel equipment tools and materials solutions
The following applications,where panel processes are also required, are not included:
o Display applications
o Photovoltaic

6
TABLE OF CONTENTS
1/2
INTRODUCTION, DEFINITIONS & METHODOLOGY………………..……2
• Report Objectives
• Who Should be Interested in this Report?
• Companies Cited in this Report
• Definitions, Limitations & Methodology
• Glossary
EXECUTIVE SUMMARY……………………………………………….………17
ADVANCED PACKAGINGTRENDS & MARKET DRIVERS……………….....32
OVERVIEW OF PANEL MANUFACTURING……………….………………...36
• Definition of Panel Level Packaging
• Overview of the Panel technologies /Key segments descriptions
• 2017-2023 Total Market forecast
• Applications targeted with Panel
• Market drivers: general motivations and drivers
• Key players activities worldwide
• Industrial players activity
• Key R&D players activity
• Commercialization Status
• Supply chain
• Overview of the players and positioning within the supply chain
FAN-OUT PANEL LEVEL PACKAGING (FOPLP)………………….68
• FOPLP players having panel manufacturing activities
• FOPLP HVM adoption: Challenges and issues
• FOPLP Panel Commercialization status & supply chain
• HVM Roadmap
• FO PLP on panel players activity
• 2017–2023 Market forecast (Revenues, units, panel starts)
EMBEDDED DIE……………………………………………..……...136
• Overview of the ED technologies
• Technology segmentation and players positioning in ecosystem
• Key players activity
• Motivations and Drivers
• 2017–2023 Market forecast (Revenues, units)
• Market dynamics
• Embedded die package volume production roadmap
• Business model & supply chain

7
TABLE OF CONTENTS
2/2
EQUIPMENT & MATERIALSTOOL-BOX …………………………………..152
 Equipment & Material for FOWLP
• Process flows,Technical gap and challenges
• Geographical map of panel equipment vendor
• Equipment suppliers and their businesses strategy and status
• Equipment vendor suppliers status for panel
• Breakdown by process step/type of equipment & Materials
• Carrier bonding / debonding
• Die attach equipment
• Molding
• RDL manufacturing
• Sputter /PVD
• Lithography
• Plating
• Thinning
• Equipment & Material for ED
• Key material suppliers and their businesses and status
• CONCLUSION & PERSPECTIVES…………………………………………152
• YOLE PRESENTATION……………………………………………………...248

REPORT METHODOLOGY
Market segmentation methodology
Market forecast methodology

REPORT METHODOLOGY
Technology analysismethodology Information collection

WHO SHOULD BE INTERESTED BY THIS REPORT (1/2)
•Equipment & material suppliers:
o To identify new business opportunities and prospects
o To understand the differentiated value of your products and technologies in this market
o To identify technology trends, challenges and precise requirements related to panel infrastructure
o To evaluate your panel packaging technologies’ market potential
o To position your company in the market
o To monitor and benchmark your competitors
•OSATs,IDMs & Foundries players:
o To understand technology trends related to panel packaging platforms
o To spot new opportunities and define diversification strategies
o To understand the overall PLP market
o To monitor and benchmark potential competitors
o To understand the supply chains including the equipment / material suppliers involved in PLP
•R&D organizations:
o To evaluate the market potential of future technologies and products for new applicative markets
o To understand the bottle necks of the PLP technology and direct their resources to solve the technical issues
o To identify the best candidates for technology transfers
o To identify the partners for the consortiums
o To monitor global activity and consolidation currently occurring in the semiconductor equipment and materials business in order to identify new
partners and targets, and make the right decisions before committing to one particular supplier

WHO SHOULD BE INTERESTED BY THIS REPORT (2/2)
•Financial & Strategic investors:
o To identify new business opportunitiesand prospects
o To understand the market potential of PLP
o To understand the various players in the supply chain that will benefit from the adoption of the PLP
o To understand about the players that are investing the PLP business
•OEMs & Integrators:
o To understand technology trends related to panel packagingplatforms
o To spot new opportunities and define diversification strategies
o To understand the overall PLP market
o To monitor and benchmark potentialcompetitors
o To understand the supply chains including the equipment / material suppliers involved in PLP

Status of Panel Level Packaging 2018 Report| Sample | www.yole.fr | ©2018
What’s new since our last
report?

PLP
WHAT’S NEW SINCE OUR STATUS OF PLP 2015 REPORT?
• We have redefined the scope of PLP. In the 2015 report,we have considered the following definition of PLP:
• If either the RDL interconnect or final assembly done at panel level, we considered it as PLP. In present report, we
consider only those packaging platform as PLP, where both the RDL interconnect fabrication and further assembly
done at panel level.
Redefined the
panel level
packagingand
its scope Current report PLP scope :
Further assembly
PANEL level
2015 report PLP scope:
RDL fabrication
Panel level Panel level OR
Strip / substrate level
=>
=>Further assemblyRDL fabrication
PLP
PLP
Further assemblyRDL fabrication
PANEL level
PANEL level Strip /substrate level
=>
*Strip size is less than 12”X12”

14
New / updated content compared to the 2015 version
What’s new?
• Updated PLP forecast 2017-2023 by different packaging platform
• Update and in depth analysisof the potential applications that could drive the PLP business
• Update of the activities of the various players involvedin PLP
• Updated the equipment and material section: In depth coverage of the processes tools & materials for
the PLP,technical challenges,key suppliers list and competitive benchmarking
• Strategies of the key players in supply chain suppliers towards the PLP business
• Different players PLP technology development,readinessand adoption time
• In depth analysis of the various manufacturingchallenges for the adoption of PLP
• Revised technology roadmap from 2017-2023

New /
updated
content
comparedto
the 2015
version
• Updated PLP forecast 2017-2023 by different packaging platform
• Update and in depth analysisof the potential applications that could drive the PLP business
• Update of the activities of the various players involvedin PLP
• Updated the equipment and material section: In depth coverage of the processes tools & materials for
the PLP,technical challenges,key suppliers list and competitive benchmarking
• Strategies of the equipment suppliers towardsthe PLP business
• Different players PLP technology development,readinessand adoption time
• In depth analysis of the various manufacturingchallenges for the adoption of PLP
• Revised technology roadmap from 2017-2023 HVMtechnology roadmap
| Panel Level Packaging 2018 Report | www.yole.fr | ©2018

Packaging Platform
Classification

PLP DEFINITION
Packaging
platform
where both
RDL & further
assembly is
done at large
panel is
considered
here as the
PLP
Packaging / Assembly process
RDL processing Further assembly
e.g Die attach, underfill/mold,testing etc.
Packagingplatform
WLCSP
FOWLP
WB
BGA/CSP
FC
BGA/CSP
3D/2.5D IC
Embedded
Die
FOPLP
Wafer level
Panel level
(on laminate/ceramic substrate / PCB)
Strip level
Wafer level Strip level
PANEL level
QFN/QFP Panel level
(on leadframe substrate) Strip level

PLP: LEVERAGE INFRASTRUCTURE FROM OTHER INDUSTRIES
PLP can utilize
the know how
and leverage
the
infrastructure
fromWLP,PCB,
LCD & solar
industries
WLP
Infrastructure
PCB /Substrate
Infrastructure
LCD
Infrastructure
Solar
Infrastructure
(PV)

19
MOTIVATIONS AND DRIVERS FOR PLP
FOPLP
(Die First)
FOPLP
(Die last)
ED in
substrate
ED in PCB
ED in flexible
board
COMPONENTS
INTEGRATION
Form factor: small footprint & low profile     
Potential for integrating several components
(SiP; SiB)     
High potential for reducing I/Os due to design   
High design flexibility & modularity     
ELECTRICAL
PERFORMANCE
Less noise: reduced parasitics because of short
interconnections     
Better thermal management   
Larger bandwidth & high speed communication 
Possibility of high I/O count 
Shielding    
PHYSICAL
PERFORMANCE
High mechanical reliability     
Physical protection of dice     
Hermiticity
Protection against harsh environment   

Key players activities
worldwide

21
BusinessModel
PLP Embedded die
FOPLP
ED in laminate ED in PCB ED in Flex
Die First RDL first
OSATs
Substrate Makers
IDMs/Foundry
R&D consortium
PLAYER POSITIONS IN THE PLP MANUFACTURING
Who is
looking at
panel
platforms
(including
development)
and players
already in
production
Various European R&D programs supported by many players
(HERMES,Hi-Level, ENSO EmPower etc.)

22
PLP MARKET FORECAST,2017-2023
By revenue (in $M)
The PLP
market will
reach $XX
M in 2023

23
READINESS FOR FOPLP-TIMELINE
NEPES,PTI
& SEMCO
will enter
production
in 2018
≤ 2016 2017 2018 2019 2020 2021 2022 2023
R&D Sampling+LVM HVM

Fan-out Panel Level Package
(FOPLP)

FAN-OUT ACTIVITIES:GLOBAL MAP OF MANUFACTURERS
Wafer & Panel-level
manufacturers
Wafer-level manufacturers
Panel-level manufacturers

26
FOPLP MARKET FORECAST (2017-2023)
In terms of revenue ($M)
The FOPLP
market is
expected to
reach
~$XXM in
2023 at an
CAGR of
XX%

27
WHICH TYPE OF PANEL?
Two main trends… Different sizes,different challenges,different success?
From Fan-Out on wafers to Fan-Out
on panel
From panel to Fan-Out on panel
• Several actors used to manufacturing panels
are willing to use their panel know-how and
aging equipment to build FO panel line.
• Several advantages:
• Most of equipment is panel-ready,no
big investment required.
• Line can be used for its initial purpose
(depending on the player,it can be
LCD,PCB or advanced substrate).
• Some concerns:
• How can resolution with such tools
compete with FO at wafer level?
• What about specific FO steps such as
molding?
This approach leads to standard sizes of PCB (e.g. 600x600mm²)
and LCD (e.g. Gen. 3 (650x550mm²)) that are currently affordable
or not used anymore.
• Fan-out specialists are willing to reduce their
costs through moving to panel
• Several advantages:
• Fan-Out process well-mastered and
specs well-established (line/space,etc..).
• Some concerns:
• Big investment to build a new line for
panel.
• How well can the process be adapted on
panel?
LCD
PCB MEOL
Wafer
615x625mm² 300x300mm²
Ex: Ex:
This approach can lead to any size of panel because lines
are new.Most likely panel size will still be derived from LCD
and PCB panels due to experience of equipment makers
anyway and equipment being cheaper.

28
FOPLP HVM ADOPTION ROADBLOCKS:TECHNICAL CHALLENGES
Key technical
challenges
associated
with panel
manufacturing

FOPLP technologies

30
VOLUME PRODUCTION ROADMAP FOR FOPLP
Key parameters
Roadmap
described here is
for volume
production and
an expected
average of the
different
technologies on
the market.
2018 2019 2020 2021
Line/Space
Package minimum
thickness (without
BGA)
Max level of RDL
Minimum die-to-die
distance
Minimum die size (X-Y
directions)
Maximum die size (X–
Y directions)
Minimum bump pitch
Maximum package
size
8*8mm² 10*10mm² 15*15mm²
2RDL 3RDL
15/15µm 10/10µm 8/8µm 5/5um
250µm 200µm 150µm
900µm 500µm 200µm
10mm 12mm 15mm
400µm 350µm
250µm 200µm

Embedded die

32
Embedding
die packaging
platforms
Embedded die in
laminate (substrate)
A die packaged between
layers of laminate which is
attached to a final PCB
Embedded die in
PCB
layers of laminate forming
the final PCB
Embedded die in
flexible substrate
layers of FLEXIBLE laminate
forming the final PCB
Embedded
interconnections in
substrate
A silicon bridge is embedded
acting as die-to-die
interconnect
EMBEDDED DIE TECHNOLOGIES SEGMENTATION
Definitions
EMIB technology from INTEL
WABE technology from Fujikura
Courtesy of AT&S
ACTIVE &
PASSIVE DICE
PASSIVE
INTERCONNECT

33
EMBEDDED DIE ACTIVITY MARKET FORECAST
Breakdown by market:revenues analysis (1/2)
In 2023,ED
packaging
revenues will
reach XX
million dollars
@2017 | www.yole.fr | Embedded die packaging: technology and market trends
2017 2018 2019 2020 2021 2022 2023
A&D and INDUSTRY 0,2 0,2 0,2 0,2 0,3 0,3 0,3
ICT 1,0 0,7 1,3 1,0 1,6 2,0 2,5
AUTOMOTIVE 0,0 0,1 0,1 0,1 0,3 0,5 1,0
CONSUMERS 0,3 0,6 0,8 1,0 1,3 1,8 2,4
MEDICAL 1,8 2,1 4,5 6,5 7,4 8,4 9,6
MOBILE 11,6 10,6 12,8 17,7 23,9 30,2 34,9
TOTAL 15,0 14,3 19,7 26,5 34,7 43,1 50,6
15,0 14,3
19,7
26,5
34,7
43,1
50,6
0,0
10,0
20,0
30,0
40,0
50,0
60,0
Market(in$M)
Embedded Die Packaging REVENUE FORECAST
2017 - 2023

34
EMBEDDED DIE PACKAGING SUPPLY CHAIN (1/3)
Examples of commercial and development partnerships

Equipment and Material
section
Overview for Panel

36
OVERVIEW OF EQUIPMENTVENDORS OFFERINGTOOLS FOR PANEL PACKAGING
Major competitors for
steppers
Scanner & Laser ablation
Major competitors for PVD
Major competitors for plating
Laser DirectImaging
Major competitors for Pick
& Place
Major competitors Compression
Molding

37
TOOL SUPPLIER STRATEGY TO ENTER PANEL BUSINESS
Equipment
supplier
entered the
panel business
by employing
different
strategies
Broadly 4
strategies
employed by
players
By organically
developing tools for
PLP from scratch
By leveragingtool
experience in other
business & upgrading itBy acquisition
Rudolph Technologies has developed tools
suitable for PLP based on the knowledge they
acquired through the acquisition of AZORES Flat
Panel Display Panel Printer.
Wait & watch
approach.Not enter till
market become big.

38
Key processes Equipment Materials
SUMMARY OF EQUIPMENT & MATERIALS SUPPLIERS INVOLVED IN FOPLP
Non exhaustive list
Carrier bonding / debonding
Pick & Place assembly
Panel level Molding

Equipment & Materials
for Embedded die
Image: Courtesy of STATS ChipPAC

40
EMBEDDED DIE PACKAGING PROCESS FLOW
Example of a Chip First « Face-Up »
• Due to the maturity of
substrate
manufacturing chain,
critical steps are
mostly those related
to the chip embedding
and resolution, and
that can potentially
impact the yield: Chip
positioning and circuit
imaging
• Those steps are critical
because they represent
challenges for PCB
industry in terms of
resolution/pitch for
packages targeting
mobile applications
Most critical
process steps
in the most
common
Embedded
Die process
flow:
Embedding in
laminate
substrate
Chip
placement/Bon
ding
Tape Lamination UV Laser drilling Cu plating
Curtain coating +
LDI – Circuit Imaging
Cu etchingTape LaminationUV Laser drilling
Cu plating
Curtain coating +
LDI – Circuit Imaging Cu etching Passivation + Balling

Status of Panel Level Packaging 2018 Report | Sample | www.yole.fr | ©2018 41
RELATED REPORTS
Discover more related reports within our bundles here.

The demand for lower cost plus higher
performance, coupled with OSAT/assembly house
end-customers’ desire for increasingly lower
prices, has driven the semiconductor industry to
develop innovative solutions. One approach to
reducing overall cost is to switch from wafer and
strip-level to a larger-size panel format that takes
advantage of efficiency and economies of scale.
Going from wafer to panel (for example 12” wafer
to 18” x 24” panel) could enable cost reductions
of up to 50% (if technologies are ready) and
yields exceeding 90%. Panel-level manufacturing
has the potential to leverage the knowledge and
infrastructure of wafer-level packaging (WLP) and
the PCB/flat-panel display/photovoltaic industries.
Various factors are driving Panel Level Packaging
(PLP) development and encouraging diverse
players from across the supply chain (including
equipment and materials) to invest in panel
infrastructure. On one side, the leading fabless
players want OSATs to reduce the cost of high-
density FOWLP and going to large size panel is
seen as the key step to significantly reducing
the package price. In fact, FOPLP is on every big
OSAT’s roadmap. On the other side are players
whose strategy is to invest and develop PLP
capability and push hard for its adoption. These
players, mainly driven by the success and publicity
surrounding FOWLP, are also those that:
• Missed the early FOWLP (eWLB) wave (i.e. PTI, ASE)
• Were affected by losses in the substrate business
and want a new business model that utilizes
their experience in substrate manufacturing (i.e.
SEMCO, Unimicron)
• Already have experience in panel processes (i.e.
LCD packaging) and believe they can leverage
this experience for PLP (i.e. NEPES)
• Want to develop high-density, low-cost
packaging to support their front-end chip
business (Samsung Electronics, Intel)
STATUS OF PANEL LEVEL PACKAGING 2018
Market Technology report - April 2018
WHY IS THE INDUSTRY INTERESTED IN PANEL LEVEL PACKAGING?
Panel level packaging players are ready for high volume production.
WHAT’S NEW
• Updated 2017 - 2023 Panel Level
Packaging (PLP) forecast, by
packaging platform
• Updated, in-depth analysis of
potential applications that could
drive the PLP business
• Update on the activities of the
various players involved in PLP
• Updated “Equipment and
Materials” section: in-depth
coverage of the processes, tools,
and materials for PLP, as well as
technical challenges, key suppliers,
and competitive benchmarking
• Equipment suppliers’ PLP-specific
strategies
• Different players’ PLP technology
development, readiness, and
adoption time
• Comprehensive analysis of the
various manufacturing challenges
for PLP adoption
• Revised technology roadmap
(based on the 2017 - 2023 high
volume manufacturing technology
roadmap)
KEY FEATURES OF THE REPORT
Get the sample of the report
on www.i-Micronews.com
• Overview of panel packaging
technologies that are available or
in-development: FOWLP panel
and embedded die
• Commercialization status, market
adoption, and potential for each
packaging technology
• Drivers and challenges for
technology adoption
• Per-player product/technology
description and analysis
• Detailed supply chain, market
adoption roadmap, and volume
forecast for each panel platform
• Panel adoption and panel
equipment readiness roadmap
• Equipment and materials challenges
(Yole Développement,April 2018)
Market drivers for panel level packaging platforms
PLP
Drivers
TECHNOLOGY
• Form factor /Thin profile
• High electrical /thermal performance
• High components integration
COST
APPLICATION
STRATEGIC MOVE
• Design flexibility
• Physical protection
• Enter the fan-out business
• New business model
• Leverage experience of
FPD/PCB/PV expertise
• High density, low cost package
solution to support front-end
business
• Higher efficiency and economies of scale
• Higher carrier usage ratio 95%
• Benefit for large package size
• Wafer to panel FO ~ 50% less cost
• Mobile / IoT /Wearables
• Automotive
• Computing
• Medical
SUPPLY CHAIN: STATUS AND READINESS
Many packaging platforms can be considered
panel-based, but for this report we consider only
two packaging technologies to be PLP, where
both RDL interconnect fabrication and further
assembly are done at panel level (with panel size
300 mm x 300 mm): FOPLP and embedded die.
Between the two, FOPLP is the most-discussed
and the one which attracts the greatest interest of
many players (including equipment and suppliers),
and thus is the main focus of this report.
Lots of players have been developing FOPLP
technology, but after years of development/
qualification/sampling, three players will
finally enter in production in 2018: Powertech
Technologies (PTI), NEPES, and SEMCO. NEPES
has been in low-volume production since 2017. ASE,
in partnership with Deca Technologies, is in the
advanced development stage and will commence
volume production in 2019/2020. Each player has
its own business strategy and is working on its
own FOPLP technology (panel size, leveraging

STATUS OF PANEL LEVEL PACKAGING 2018
TECHNICAL CHALLENGES AND HIGH VOLUME MANUFACTURING ROADMAP FOR
PANEL LEVEL PACKAGING
Certain criteria must be fulfilled and certain challenges
overcome for FOPLP’s broad adoption. These criteria/
challenges are linked to large capex investment,
standardization, multisource availability, and most
importantly, market availability to keep the panel line
running. There are technical challenges too, such as
warpage control, die placement accuracy, and the
fabrication of sub 10/10um line, etc. on large panels.
Standardization of the panel size and assembly process
is the biggest hurdle for FOPLP adoption. Each player
is developing its own process using different panel sizes
and infrastructure (PCB/LCD/WLP/PV/Mix) catering
to specific applications and customers. In this scenario
it’s very difficult for end-customers to multisource.
Also, it’s not profitable for equipment suppliers to
design and manufacture equipment according to
different customers’ requirements.
Given the technical challenges that will adversely affect
the yield, the FOPLP that go into HVM production will
support a relatively simple design: 10/10 umL/S, 10 x
10 mm2
package size, Max 2L RDL. With the maturation
of the technology and the experience gained, FOPLP
will eventually be adopted for high-density design with
10/10um L/S, multi-layer RDL, 15 x 15mm2
package
size, and multi-die SiP integration.
different infrastructure, etc.). For example, NEPES is
focused on the coarse design (10/10 L/S), targeting
automotive, sensors, and IoT applications, and will
likely not explore high-density design. On the other
hand, PTI and SEMCO’s long-term aim is to target
mid and high-end applications that require 8/8 or less
L/S. Meanwhile, Unimicron is working on a business
model whereby it will manufacture the high-density
RDL, with further assembly done by an OSAT partner
or customer. Also, prominent OSATs like Amkor and
JCET/STATS ChipPAC are currently in a “wait and
see” stage, evaluating various options. They will not
enter volume production before 2022.
Equipment availability for PLP is not a bottleneck today.
Tools are available in the market to support various
process steps in panel processing. However, certain tools
that support high-density panel packaging are special and
expensive. So, tool cost, not availability, is the bottleneck.
For some panel-producing process steps (plating, physical
vapor deposition [PVD], molding, die attach, and dicing),
tools are readily available and can be adapted from the
PCB, flat-panel display, or LCD industries. However, for
other key process steps inherent to advanced packaging
(i.e. lithography), the development of new, upgraded tool
capabilities is necessary to support such steps as fine
L/S patterning on panel, thick-resist lithography, panel-
handling capabilities, exposure field size, and depth of
focus. Over the last few years, these tools have been in
development at equipment suppliers.
Equipment suppliers are adopting different strategies
for entering the PLP business: acquisition (for example,
Rudolph Technologies has developed PLP-focused tools
based on knowledge received through its acquisition of
AZORES Flat Panel Display Panel Printer); by leveraging
tool experience from other businesses and upgrading
it (i.e. Evatec, Atotech, SCREEN); and by organically
developing PLP tools from scratch (ASM). Also, some
tool suppliers have a strong position in the FOWLP
market but are skeptical of the PLP business and thus
are taking a wait-and-see approach (Ultratech, Applied
Materials, Lam Research).
Tool supplier strategies to enter panel business
Broadly 4
strategies
employed by
players
By organically developing
tools for Panel Level
Packaging from scratch
By leveraging tool
experience in other
business upgrading itBy acquisition
Wait watch
approach. Not enter till
market becomes big.
Non exhaustive list of companies
Before
2016
2017 2018 2019 2020 2021 2022
NEPES, PTI SEMCO will enter production in 2018
RD Sampling + LowVolume Manufacturing HighVolume Manufacturing
Non exhaustive list of companies
Timeline: Readiness for fan-out panel level packaging

Find more
details about
this report here:
MARKET TECHNOLOGY REPORT
COMPANIES CITED IN THE REPORT (non exhaustive list)
AMS, Amicra Microtechnologies, Amkor, Analog Devices, Apple, Applied Materials, Asahi Kasei, ASE,
ASM Pacific, ATS, Atotech, AVX, Besi, Bosch, Canon, CEA-LETI, Continental, Dai Nippon, Daimler,
DNP, DYCONEX AG, Dow Electronic Materials, Evatec, EVG Group, Ford, Fujikura, GaN Systems,
General Electric, Hanmi, HD Micro/DuPont, Heidelberg Instruments, HighTec EDV System,Huawei,
Ibiden, Infineon, Intel, IPDiA, IME A*Star, IMEC, ITRI, IZM Fraunhofer, J-Devices, JSR Micro, Kulicke
Soffa (KS), Kyocera, Maxim, Merck/AZ EM, Mitsui Kinzoku,Murata Electronics, Nagase, Nanium, NCAP
China, Nikon, Nitto Denko, ON Semiconductor, Orbotech, ORC, Panasonic, Powertech Technologies,
Qorvo, Qualcomm, Rohm Semiconductor, Rudolph, Sarda Technologies, Schweizer, SCREEN, Shinko,
Shin Etsu, STMicroelectronics, SUSS MicroTec, Taiyo Yuden, Tazmo, TCL, TDK-EPCOS, TEL, Texas
Instruments (TI), Thales, Towa, TransSiP, Tokyo Ohka Kogyo Co., LTD. (TOK), TSMC, Shin-Etsu
MicroSi, Samsung Electro Mechanics (SEMCO), STATS ChipPAC, Ultratech, Unimicron, USHIO,UTAC,
Valeo, Vishay, Yamada and many more…
AUTHOR
Santosh Kumar is currently working
as Senior Technology Market Research
Analyst at Yole Développement, the «More
than Moore» market research and strategy
consulting company. He worked as senior
RD engineer at MK Electron Co. Ltd
where he was engaged in the electronics
packaging materials development and
technical marketing. His main interest areas
are advanced electronic packaging materials
and technology including TSV and 3D
packaging, modeling and simulation, reliability
and material characterization, wire bonding
and novel solder materials and process etc.
He received the bachelor and master degree
in engineering from the Indian Institute of
Technology (IIT), Roorkee and University of
Seoul respectively. He has published more
than 20 papers in peer reviewed journals and
has obtained 2 patents. He has presented
and given talks at numerous conferences and
technical symposiums related to advanced
microelectronics packaging.

Introduction, definitions and methodology 2
Report objectives
Who should be interested in this report?
Companies cited in this report
Definitions, limitations and methodology
Glossary
What’s new since last report ?
Executive summary 17
Advanced packaging trends and market drivers 32
Overview of panel manufacturing 36
Definition of Panel Level Packaging
Overview of the Panel technologies /Key
segments descriptions
2017-2023 total market forecast
(revenues, units)
Applications targeted with Panel
Market drivers: general motivations and drivers
Key players activities worldwide
Industrial players activity
Key RD players activity
Commercialization status
Supply chain
Fan-Out Panel Level Packaging (FOPLP) 68
FOPLP players having panel manufacturing
activities
Key challenges
FOPLP HVM adoption issues
FOPLP Panel commercialization status
and supply chain
2017–2023 market forecast (revenues, units,
panel starts)
Embedded Die 136
Overview of the ED technologies
Key players activity
Motivations and drivers
2017–2023 market forecast (revenues, units)
Market dynamics
Embedded die package volume production
roadmap
Business model supply chain
Equipment and materials tool-box 152
Equipment and material for FOPLP
Equipment and material for ED
Conclusion and perspectives 248
TABLE OF CONTENTS (complete content on i-Micronews.com)
Roadmap: volume production for fan-out panel level packaging
OBJECTIVES OF THE REPORT
• Provide an overview of panel package technologies
• Describe the key applications that could use the panel infrastructure
• Highlight panel package solutions and the players supporting these packages
• Identify the current and future industrial players for each packaging technology, based on panel level
• Provide market data and forecasts for panel products
• Explore each segment’s competitive landscape
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• Status of Advanced Substrates 2018:
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Sensor
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2018 2019 2020 2021
Line/Space
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Minimum die-to-die distance
Minimum die size
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Maximum die size
(X–Y directions)
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Maximum package size 8*8mm 10*10mm 15*15mm
2RDL 3RDL
15/15 m 10/10 m 8/8 m 5/5um
250 m 200 m 150 m
900 m 500 m 200 m
10mm 12mm 15mm
400 m 350 m
250 m 200 m

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REPORTS COLLECTION
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• MEMS Sensors
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• Imaging
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• Photonics
• Advanced packaging
• Manufacturing
• Advanced substrates
• Power electronics
• Batteries and energy management
• Compound semiconductors
• Solid state lighting
• Displays
• Software
• Memory

OUR 2018 REPORTS COLLECTION (1/3)
MEMS SENSORS
o MARKET AND TECHNOLOGY REPORT – by Yole Développement
− Status of the MEMS Industry 2018 - Update
− Silicon Photonics 2018 - Update
− Consumer Biometrics: Sensors Software 2018 - Update
− MEMS Pressure Sensors 2018
− Air Quality Sensors 2018
o REVERSE ENGINEERING COSTING REVIEW – by System Plus Consulting
− Gas Particles Sensors
− MEMS Pressure Sensors
− Piezo MEMS 2018 *
o PATENT ANALYSES – by KnowMade
− MEMS Microphone – Patent Landscape Analysis
RF DEVICES ANDTECHNOLOGIES
o MARKET AND TECHNOLOGY REPORT – byYole Développement
− 5G impact on RF Front End Modules and Connectivity for Cellphones 2018 – Update
− Radar Technologies for Automotive 2018 - Update
− RF GaN Market: Applications, Players, Technology, and Substrates 2018-2023 –
Update
− Advanced RF System-in-Package for Cellphones 2018 – Update *
− Wireless technologies (Radar, V2X) for Automotive 2018
− RF Standards and Technologies for Connected Objects 2018
− RF Photonic Components Technologies for 5G Infrastructure 2018
− RF Front-End Modules in Smartphones
− RF GaN*
− RF Front End Module – Patent Landscape Analysis
− RF GaN – Patent Landscape Analysis
IMAGING OPTOELECTRONICS
− Status of the CMOS Image Sensor Industry 2018 – Update
− Status of the Compact Camera Module and Wafer Level Optics Industry 2018 -
Update
− 3D Imaging and Sensing 2018 - Update
− Machine Vision for Industry and Automation 2018
− Sensors for Robotic Vehicles 2018
− Imagers and Detectors for Security and Smart Buildings 2018
− LiDARs 2018
o QUARTERLY UPDATE – by Yole Développement
− CMOS Image Sensors 2018 *
− CMOS Image Sensors
− Compact Camera Modules
− LiDAR – Patent Landscape Analysis
SOFTWARE
− Consumer Biometrics: Sensors Software 2018 - Update
− Processing Hardware and Software for AI 2018 – Vol. 1 2
Update : 2017 version still available / *To be confirmed

ADVANCED PACKAGING
− Status of Advanced Packaging Industry 2018 - Update
− Status of Advanced Substrates 2018: Embedded Die and Interconnects, Substrate Like
PCB Trends
− Fan-Out Packaging 2018 – Update*
− 3D TSV and Monolithic Business Update 2018 – Update
− Advanced RF System-in-Package for Cellphones 2018 – Update*
− Power Modules Packaging 2018 – Update
− Discrete Power Packaging 2018 – Update*
− Memory Packaging Market and Technology Report 2018 – Update*
− Status of Panel Level Packaging 2018
− Trends in Automotive for Advanced Packaging 2018
− Processing Hardware and Software for AI 2018 – Vol. 1 2
− Integrated Passive Devices (IPD) 2018
− RF Front-End SiP
− Fan-Out Packaging *
− Hybrid Bonding for 3D Stack – Patent Landscape Analysis
MANUFACTURING
− Wafer Starts for More Than Moore Applications
− Equipment for More than Moore: Technology Market Trends for Lithography
Bonding/Debonding 2018
− Equipment for More than Moore: Technology Market Trends for Thin Film
Deposition Etching 2018
− Wafer Bonding Technology Overview 2018
MEMORY
− Emerging Non Volatile Memory 2018 – Update
− Memory Packaging Market and Technology Report 2018 – Update*
o QUARTERLY UPDATE – by Yole Développement**
− Memory Market 2018 (NAND DRAM)
o MONTHLY UPDATE – by Yole Développement**
− Memory Pricing 2018 (NAND DRAM)
− DRAM Technology Cost Review 2018
− NAND Memory Technology Cost Review 2018
− 3D Non-Volatile Memories – Patent Landscape Analysis
COMPOUND SEMICONDUCTORS
MARKET AND TECHNOLOGY REPORT – byYole Développement
− Status of Compound Semiconductor Industry 2018*
− Power SiC 2018: Materials, Devices, and Applications - Update
− Power GaN 2018: Materials, Devices, and Applications – Update
− RF GaN Market: Applications, Players, Technology, and Substrates 2018-2023 –
Update
− GaAs Materials, Devices and Applications 2018
− InP Materials, Devices and Applications 2018
− Power SiC Devices
− Power GaN Devices
− Power SiC – Patent Landscape Analysis
− Status of the GaN IP – Patent Watch 2018 Patent Activity 2017
Update : 2017 version still available / *To be confirmed / ** Can not be selected within an Annual Subscription offer

POWER ELECTRONICS
MARKET AND TECHNOLOGY REPORT – by Yole Développement
− Status of Power Electronics Industry 2018 - Update
− Power Modules Packaging 2018 - Update
− Discrete Power Packaging 2018 – Update*
− Power Electronics for EV/HEV 2018 - Update
− Wireless Charging Market Expectations and Technology Trends 2018
− Integrated Passive Devices (IPD) 2018
− Power ICs Market 2018 – Update
− Power ICs Market 2018*
− Power Modules*
BATTERY AND ENERGY MANAGEMENT
− Solid State Electrolyte Battery 2018
− Li-ion Battery Packs for Automotive and Stationary Storage Applications 2018 -
Update
− Solid-State Batteries – Patent Landscape Analysis
− Status of the Battery IP – Patent Watch 2018 Patent Activity 2017
SOLID STATE LIGHTING
− IR LEDs and Lasers 2018 - Update
− Automotive Lighting 2018 – Update
− UV LEDs 2018 - Update
− VCSELs 2018
− LiFi 2018
− VCSELs 2018
− UV LEDs 2018 *
DISPLAYS
− MicroLED Displays 2018 – Update
− Quantum Dots and Wide Color Gamut Display Technologies 2018 - Update
− Displays and Optical Vision Systems for AR / VR / MR 2018
− MicroLED Display – Patent Landscape Analysis
MEDTECH
− BioMEMS Non Invasive Emerging Biosensors: Microsystems for Medial
Applications 2018 - Update
− Point-of-Need Testing: Application of Microfluidic Technologies - Update
− Neurotechnologies and Brain Computer Interface 2018
− CRISPR-Cas9 Technology: From Lab to Industries 2018
− Portable Medical Imaging 2018
− Inkjet Functional and Additive Manufacturing for Electronics 2018
− Liquid Biopsy 2018: From Isolation to Downstream Applications
− Chinese Microfluidics Industry 2018
− Scientific Cameras for the Life Sciences Analytical Instrumentation Laboratory
Markets 2018*
− Microfluidic IC Cooling – Patent Landscape Analysis
− Circulating Tumor Cell Isolation – Patent Landscape Analysis
− Organ-on-a-Chip – Patent Landscape Analysis
− OCT Medical Imaging – Patent Landscape Analysis
Update : 2017 version still available / *To be confirmed

OUR 2017 PUBLISHED REPORTS (1/3)
MEMS SENSORS
− Status of the MEMS Industry 2017
− High End Inertial Systems Market and Technology 2017
− Magnetic Sensors Market and Technologies 2017
− MEMS and Sensors for Automotive - Market and Technology Trends 2017
− Acoustic MEMS and Audio Solutions 2017
− Sensors and Sensing Modules for Smart Homes and Buildings 2017
− Fingerprint Sensor Applications and Technologies – Consumer Market Focus 2017
o REVERSE COSTING REPORT – by System Plus Consulting
− Continental SRL1: State-of-the-art LiDAR for Advanced Driver Assistance Systems –
Reverse Costing Report
− Bosch Mobility Ultrasonic Sensor – Reverse Costing Report
− MEMS Packaging 2017 - Reverse Costing Review
− Bosch BMP380 Pressure Sensor – Reverse Costing Report
IMAGING PHOTONICS
− Status of the CMOS Image Sensor Industry 2017
− 3D Imaging and Sensing 2017
− Uncooled Infrared Imaging Technology Market Trends 2017
− Camera Module Industry Market and Technology Trends 2017
− FLIR Boson – a small, innovative, low power, smart thermal camera core – Reverse
Costing Report
− Camera Module Physical Analyses Overview 2017
RF DEVICES ANDTECHNOLOGIES
− RF Front End Modules and Components for Cellphones 2017
− Advanced RF System-in-Package for Cell Phones 2017
− 5G Impact on RF Front-End Industry 2017
ADVANCED PACKAGING
− Status of the Advanced Packaging Industry 2017
− Embedded Die Packaging: Technology and Market Trends 2017
− Fan-Out: Technologies and Market trends 2017
− Advanced Substrates Overview: From IC Package to Board 2017
− 3D TSV and 2.5D Business Update - Market and Technology Trends 2017
− Advanced RF System-in-Package for Cellphones 2017
− Memory Packaging Market and Technology Report 2017
− MEMS Packaging 2017
− Emerging Non-Volatile Memory 2017
− NVIDIA Tesla P100 - Reverse Costing Report
− MEMS Packaging - Reverse Technology Review
− Advanced RF SiP for Cellphones 2017 - Reverse Costing Review
SOFTWARE
− Embedded Software in Vision Systems
MEDTECH
− Status of the Microfluidics Industry 2017
− Solid-State Medical Imaging 2017
− Organs-On-Chips 2017
− Connected Medical Devices Market and Business Models 2017
− Artificial Organ Technology and Market analysis 2017
− Medical Robotics Technology Market Analysis 2017

OUR 2017 PUBLISHED REPORTS (2/3)
MANUFACTURING
− Laser Technologies for Semiconductor Manufacturing 2017
− Equipment and Materials for 3D TSV Applications 2017
− Equipment and Materials for Fan-Out Packaging 2017
− Glass Substrate Manufacturing in the Semiconductor Field 2017
BATTERIES ENERGY MANAGEMENT
− Status of the Rechargeable Li-ion Battery Industry
− Market Opportunities for Thermal Management Components in Smartphones
DISPLAYS
− MicroLED Displays
− Quantum Dots and Wide Color Gamut Display Technologies
− Phosphors Quantum Dots 2017 - LED Downconverters for Lighting Displays
SOLID STATE LIGHTING
− LED Packaging 2017: Market, Technology and Industry Landscape
− CSP LED Lighting Modules
− IR LEDS and VCSELs - Technology, Applications and Industry Trends
− LED Lighting Module Technology, Industry and Market Trends 2017
− Automotive Lighting: Technology, Industry and Market Trends 2017
− Horticultural LED Lighting: Market, Industry, and Technology Trends
POWER ELECTRONICS
− Status of the Power Electronics Industry 2017
− Thermal Management Technology and Market Perspectives in Power Electronics and
LEDs 2017
− Gate Driver Market and Technology Trends 2017
− Power MOSFET 2017: Market and Technology Trends
− Power Module Packaging: Material Market and Technology Trends 2017
− IGBT Market and Technology Trends 2017
− Power Management ICs Market 2017
− EPC2045 100V GaN-on-Silicon Transistor – Reverse Costing Report
− Silicon Capacitor - Technology and Cost Review
− Industrial 100V MOSFET - Technology and Cost Review
− InvenSense ICM-20789: High Performance 6-Axis Motion Sensor and Pressure Sensor
Combo – Reverse Costing Report
COMPOUND SEMICONDUCTORS
− Bulk GaN Substrate Market 2017
− RF Power Market and Technologies 2017: GaN, GaAs and LDMOS
− Power SiC 2017: Materials, Devices, Modules, and Applications
− Power GaN 2017: Epitaxy, Devices, Applications, and Technology Trends

OUR 2017 PUBLISHED REPORTS LIST (3/3)
OUR PARTNERS’ REPORTS
PATENT ANALYSES – by KnowMade
− Wireless Charging Patent Landscape Analysis
− RF Acoustic Wave Filters Patent Landscape Analysis
− NMC Lithium-Ion Batteries Patent Landscape Analysis
− Pumps for Microfluidic Devices Patent Landscape
− III-N PatentWatch
− FLUIDIGM Patent Portfolio Analysis
− Knowles MEMS Microphones in Apple iPhone 7 Plus Patent-to-Product Mapping 2017
− Consumer Physics SCiO Molecular Sensor Patent-to-Product Mapping
− Patent Licensing Companies in the Semiconductor Market - Patent Litigation Risk and Potential Targets
− MicrofluidicTechnologies for Diagnostic Applications Patent Landscape
TEARDOWN REVERSE COSTING – by System Plus Consulting
More than 60 teardowns and reverse costing analysis and cost simulation tools published in 2017
MORE INFORMATION
o All the published reports from theYole Group of Companies are available on our website www.i-Micronews.com.
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Email: laferriere@yole.fr – + 1 310 600-8267
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Email: onozawa@yole.fr - +81 34405-9204
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Email: wang@yole.fr - +886 979 336 809
• Europe: Lizzie Levenez, EMEA Business Development Manager
Email: levenez@yole.fr - +49 15 123 544 182
• RoW: Jean-Christophe Eloy, CEO President,Yole Développement
Email eloy@yole.fr - +33 4 72 83 01 80
o FINANCIAL SERVICES (in partnership withWoodside
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Status of Panel Level Packaging 2018 Report by Yole Developpement

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