Se ha denunciado esta presentación.
Utilizamos tu perfil de LinkedIn y tus datos de actividad para personalizar los anuncios y mostrarte publicidad más relevante. Puedes cambiar tus preferencias de publicidad en cualquier momento.

12 memory hierarchy

951 visualizaciones

Publicado el

  • Sé el primero en comentar

12 memory hierarchy

  1. 1. Ch. 12 Cache Direct Mapped Cache
  2. 2. Memory Hierarchy Registers: very few, very fast cache memory: small, fast main memory: large, slow secondary memory (disk): huge, very slow Example: http://www.dell.com/content/products/category.aspx/vostrodt? c=us&cs=04&l=en&s=bsd Comp Sci 251 -- mem hierarchy 2
  3. 3. Memory Hierarchy Registers: very small, very fast cache memory: small, fast  Up to Intel® CoreTM 2 Duo E6700 (2.60GHz, 4MB L2 cache, 1066MHz FSB) main memory: large, slow  Up to 4GB1 Dual-Channel DDR22 SDRAM3 (667MHz) secondary memory (disk): huge, very slow  Up to 2 hard drives and 1 TB of data Comp Sci 251 -- mem hierarchy 3
  4. 4. Goal: Illusion of Large Fast MemoryExploit two characteristics of programs: Temporal locality: programs tend to re- access recently accessed locations Spatial locality: programs tend to access neighbors of recently accessed locations Comp Sci 251 -- mem hierarchy 4
  5. 5. Exploiting Locality Keep most recently accessed items and their neighbors in faster memory We will focus on the cache/main memory interface Comp Sci 251 -- mem hierarchy 5
  6. 6. Terminology Cache hit  word we want to access is already in cache  transaction is fast Cache miss  word we want is not in cache  main memory access is necessary  transaction is slow Comp Sci 251 -- mem hierarchy 6
  7. 7. Hit or Miss?Two questions on each memory access: Is the requested word in cache? Where in cache is it?Cache block contains: copy of main memory word(s) info about where word(s) came from(Note: cache block can contain >1 memory word) Comp Sci 251 -- mem hierarchy 7
  8. 8. Direct Mapped Cache Each memory word maps to a single cache block “round robin” assignment of words to blocks (assume one-word blocks for now, byte- addressable memory) How do we tell which block a word maps to? number of cache blocks is a power of 2 Comp Sci 251 -- mem hierarchy 8
  9. 9. Direct Mapped Cache Memory Memory Address data Cache Memory address data Comp Sci 251 -- mem hierarchy 9
  10. 10. Direct Mapped Cache CacheMainMemory MemoryIndex IndexIndex0 Index0Index1 Index1Index2 Index2Index3 Index3Index4Index5Index6Index7Index8Index9 Comp Sci 251 -- mem hierarchy 10
  11. 11. Direct Mapped Cache If cache has 2n blocks, cache block index = n bitsmain memory address: Tag cache index 00 leftover bits are stored in cache as a tag Cache block format:Cache index V Tag Data Comp Sci 251 -- mem hierarchy 11
  12. 12. Cache Read Operation Look up cache block indexed by low n bits of address Compare Tag in cache with Tag bits of address if valid and match: HIT  read from cache mismatch or invalid: MISS  new word + Tag is brought into cache Comp Sci 251 -- mem hierarchy 12
  13. 13. Cache Write Operation(Problem: main memory and cache can become inconsistent) Look up cache block indexed by low n bits of address Compare Tag with high bits of address if valid and match: HIT  write cache and main memory (write-through policy) invalid or mismatch: MISS  write main memory  overwrite cache with new word + Tag Comp Sci 251 -- mem hierarchy 13
  14. 14. Exercise Byte-addressable main memory 32-bit main memory addresses 1024KB-capacity cache; one word per cache block  256K = 218 cache blocks Show cache block format & address decomposition Access memory address 0x0040006c  Which cache block?  What tag bits? Comp Sci 251 -- mem hierarchy 14
  15. 15. Cache Block Size A cache block may contain > 1 main memory word (why is this a good idea?) Example:  byte-addressable memory  4-word cache block Address: | block address |offset|00 |tag|cache index|offset|00 Comp Sci 251 -- mem hierarchy 15
  16. 16. Exercise Byte-addressable main memory 32-bit main memory addresses 1024KB-capacity cache; four words per cache block  64K=216 cache blocks Show cache block format & address decomposition Access memory address 0x0040006c  Which cache block?  What tag bits? Comp Sci 251 -- mem hierarchy 16
  17. 17. Given main memory of 256 bytes, a memory block is one word, cache size (number of blocks ) is 8 What is the total size of the cacheAddress (binary) Contents (Hex) in bits?000000 aa bb cc dd Memory address is m bytes long000100 00 11 00 33 256 bytes = 2m bytes → m = ?001000 ff ee 01 23001100 45 67 89 0a010000 bc de f0 1a You need n bits to address 8010100 2a 3a 4a 5a blocks in cache. n = ?011000 6a 7a 8a 9a011100 1b 2b 3b 4b100000 b2 b3 b4 b5 You need b bits to address 4 bytes100100 c1 c2 c3 c4 in a word. b = ?101000 d1 d2 d3 d4101100 e1 e2 e3 e4110000 f1 f2 f3 f4 Size of tag bits = t = m - n - b110100 a1 a2 a3 a4 Size of cache = (1+ t + 32) x 8111000 2c 3c 4c 5c111100 2d 3d 4d 5d Comp Sci 251 -- mem hierarchy 17
  18. 18. Given main memory of 256 bytes, a memory block is 2 words, cache size is 8Address (binary) Contents (Hex) What is the total size of the000000 aa bb cc dd cache in bits?000100 00 11 00 33 Memory address is m bytes long001000 ff ee 01 23 256 bytes = 2m bytes → m = ?001100 45 67 89 0a010000 bc de f0 1a You need n bits to address 8010100 2a 3a 4a 5a blocks in cache. n = ?011000 6a 7a 8a 9a011100 1b 2b 3b 4b You need b bits to address the100000 b2 b3 b4 b5 bytes in 2 words. b = ?100100 c1 c2 c3 c4101000 d1 d2 d3 d4 Size of tag bits = t = m - n – b101100 e1 e2 e3 e4 Size of cache = (1+ t + 64) x 8110000 f1 f2 f3 f4110100 a1 a2 a3 a4111000 2c 3c 4c 5c111100 2d 3d 4d 5d Comp Sci 251 -- mem hierarchy 18
  19. 19. Suppose a memory address is 32 bits, a memory block is 8 words and thecache size is 16K blocks. What is the total size of the cache in bytes? 32-bit Memory addressCache v Tag Data in 8-word block 16K blocks Comp Sci 251 -- mem hierarchy 19

×