1. Abhishek Bhattacharjee
Ph.D Student, Microelectronics and VLSI group +91 8791671065/8011319750
Electronics and Communication Engineering Dept. abhi8.dec2014@iitr.ac.in
Indian Institute of Technology, Roorkee abhishek89.187@gmail.com
Academic Details
Year Degree Institute Percentage/CGPA
2014-
Present
Ph.D in Electronics and
Communication Engineering
Indian Institute of Technology Roorkee
__________
2014
M.Tech in Microelectronics and
VLSI Design
National Institute of Technology Silchar CPI=9.35/10
2011
B.Tech in Electronics and
Communication Engineering
National Institute of Technology
Agartala
CPI=8.17/10
2007
Class XII
CBSE AISSCE
Ramakrishna Mission Vidyalaya
Agartala
85.40%
2005
Class X
CBSE AISSE
Pranavananda Vidyamandir Agartala 82.80%
Objective
To pursue my graduate studies in Electronics and Communication Engineering leading to a career in teaching
and research.
Major Projects
 Characteristics study and modelling of SINWFET’s Dr. S. Dasgupta
and their applications in digital logic IIT Roorkee
P.hD Project July 2014- present
As the semiconductor industry is thriving on scaling of bulk planar MOS devices there is an urge of next
generation of ultra thin devices family which can replace the low stand by power FINFET devices. The
obvious choice is Silicon nanowire FET. I am trying to model different attributes of this device analytically
and verify the results using SYNOPSYS TCAD.
 DC and Microwave Characteristics Study of InAlN/GaN based HEMT Dr. T.R. Lenka
NIT Silchar
M.Tech Project January 2013-May 2014
Group III-V semiconductors are the materials of interest for high power and high speed switching
activities. They are forming the backbone of the future multi trillion semiconductor industry by taking
part in the formation of devices like HBT's, LASER’s, LED, Sensors/Photodetector's, HEMT’s and so on so
forth. I worked on AlGaN/GaN, InAlN/(AlN)/GaN HEMT's in which I tried to improve the operating speed
by increasing the 'FIGURE OF MERIT' or Ion/Ioff ratio in those devices. All the works were performed in
SILVACO platform of Technology Computer Aided Design, or TCAD.

2.  Development of Booth’s multiplier using Verilog HDL Dr. S. Pradhan
NIT Agartala
B.Tech Project July 2010-May 2011
I worked on the Verilog coding of the implementation of a new architectural design of Booth’s
multiplier algorithm and the proposed design showed significant improvement in terms of power
consumption than the existing one.
 Automatic Traffic Controller ERTL
Electronics Regional Test Laboratory
Pre Final Year Project May 2010-July 2010
I worked on the Verilog coding of a small LED based ATC (Automatic Traffic Controller) design; tried to
implement the same by dumping the code into FPGA.
Scholastic Achievements
 Will receive MHRD scholarship during P.hd at Indian Institute of Technology, Roorkee from 2014-
2018.
 Received MHRD scholarship during M.Tech at National Institute of Technology, Silchar from 2012-
2014.
 Qualified GATE 2012 with 97.20 percentile in UR category.
 Qualified GATE 2013 with 91.94 percentile in UR category.
 Qualified GATE 2014 with 88.59 percentile in UR category.
Member of Professional Bodies
 Student member of IEEE (USA) (Electron Devices Society) (membership no-92615139) since 15-03-
2013.
 Member of IAENG (International Association of Engineers) (membership no-132789) since 29-08-2013.
Seminar’s and Workshop’s
 Acted as Coordinator in IEEE EDS Workshop on “MEMS PROTOTYPING, RF MEMs
FABRICATION, DESIGN AND MODELLING” held on 9th
May, 2015 at Department of E&C, IIT
Roorkee.
 Attended IEEE CAS Workshop on “ADVANCED TOPICS IN VLSI CIRCUIT DESIGN” held on 18th
and 19th
October, 2014 at Department of E&C, IIT Roorkee.
 Attended IEEE-EDS Mini-Colloquium on “NANOSCALE DEVICE PHYSICS AND RELIABILITY”
held on 19th
September, 2014 at Department of E&C, IIT Roorkee.

3.  Attended 3 day’s Workshop on “APPLICATION OF ENBEDDED SYSTEM IN DIFFERENT
VARIOUS FIELD OF ELECTRONICS” held at NIT, Silchar during 28th
-30th
September, 2012 under
TEQIP-II.
 Attended two days seminar on “MEMS AND SENSORS” held on 11-12 September, 2013 which was
organized by IEEE-EDS student branch chapter held at NIT Silchar under TEQIP-II.
 Attended one day seminar on “INTERDISCIPLINARY RESEARCH ON BIOMEDICAL ENGG” held
on 26th August, 2013 which was organized by IEEE-EDS student branch chapter held at NIT Silchar
under TEQIP-II.
 Attended 1 day talk on “CMOS CIRCUIT FOR BIOMEDICAL APPLICATION” organized by Dept.
of ECE, NIT Silchar on 13th
Dec, 2012 under TEQIP-II.
Publications
 Book Chapter
1. D. Pandey, A. Bhattacharjee and T.R Lenka ‘Study on temperature dependence scattering
mechanisms and mobility effects in GaN and GaAs HEMT’s’, Physics of Semiconductor
Devices, Environmental Science and Engineering (IWPSD 2013), ISBN-978-3-319-03001-2,
DOI-10.1007/978-3-319-03002-9_15,pp.67-70 (Springer).
 International Conferences
1. A. Bhattacharjee and T.R Lenka ‘RF and Microwave Characteristics of a 20nm Gate length
In0.2Al0.8N/GaN Based HEMT Having a High ‘Figure of Merit’, 2nd
IEEE International
Conference on Devices, Circuits and Systems (ICDCS 2014) organized by Karunya University,
Coimbatore, Tamil Nadu, March,2014 (IEEE Xplore).
2. A. Bhattacharjee and T.R Lenka ‘Insight to the 2DEG Transport and mobility Effects of a
20nm recessed Gate InAlN/GaN/AlN HEMT.’ IEEE International Conference on Electronics
and Communication Systems (ICECS 2014), organized by Karpagam College of Engineering,
Mayileripalayam, Tamil Nadu, Feb,2014 (IEEE Xplore).
 International Journals
1. A. Bhattacharjee, M. Saikiran, A. Dutta, Bulusu A and S. Dasgupta ‘Spacer Engineering-Based
High-Performance Reconfigurable FET with Low OFF Current Characteristics’, IEEE
Electron Device Letters, Vol.36(5), 2015 (IEEE Xplore).

4. 2. A. Bhattacharjee and T.R Lenka ‘Performance Analysis of a 20nm Gate length In0.2Al0.8N/GaN
HEMT with Cu-Gate having a remarkable high ION/IOFF Ratio’, Journal of Semiconductors,
Vol. 35(6), 2014 (IOP Science).
3. Abhishek Bhattacharjee, Sandeep Kumar, Devashish Pandey and Trupti Ranjan Lenka ‘An
Investigation of Novel Characteristics of Ultrathin Al0.2Ga0.8N/GaN MOSHEMT Having 20nm
Gate Length and SiO2 Gate Dielectric, Journal of Electron Devices, Vol.19, pp-1674-
1679,2014 (France).
Computer Forte
Design languages : Mat lab, P Spice, XILINX, Model SIM, Cadence, and T-cad.
Operating Systems : Windows 98/XP/2000/2007.
Computer Languages: C, Verilog HDL.
Area of Interest : Semiconductor Device Modelling
Subject of interest : Semiconductor Device Physics, Digital VLSI circuits, Nanoelectronics
References
1. Dr. Sudeb Dasgupta, Associate Professor, Dept. of Electronics and Communication Engg, IIT
Roorkee, +91 1332-285666, sudebfec@iitr.ac.in.
2. Dr. Anand Bulusu, Associate Professor, Dept. of Electronics and Communication Engg, IIT
Roorkee, +91 1332-245347, anandfec@iitr.ac.in.