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VHDL Reference
1.
E&CE 327: Digital
Systems Engineering Course Notes (with Solutions) Mark Aagaard 2011t1–Winter University of Waterloo Dept of Electrical and Computer Engineering
2.
3.
Contents I Course Notes
1 1 VHDL 3 1.1 Introduction to VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.1 Levels of Abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.2 VHDL Origins and History . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.3 Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.4 Synthesis of a Simulation-Based Language . . . . . . . . . . . . . . . . . 7 1.1.5 Solution to Synthesis Sanity . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.6 Standard Logic 1164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 Comparison of VHDL to Other Hardware Description Languages . . . . . . . . . 9 1.2.1 VHDL Disadvantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.2 VHDL Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.3 VHDL and Other Languages . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.3.1 VHDL vs Verilog . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.3.2 VHDL vs System Verilog . . . . . . . . . . . . . . . . . . . . . 10 1.2.3.3 VHDL vs SystemC . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.3.4 Summary of VHDL Evaluation . . . . . . . . . . . . . . . . . . 11 1.3 Overview of Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.1 Syntactic Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.2 Library Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.3 Entities and Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3.4 Concurrent Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3.5 Component Declaration and Instantiations . . . . . . . . . . . . . . . . . . 16 1.3.6 Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.3.7 Sequential Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3.8 A Few More Miscellaneous VHDL Features . . . . . . . . . . . . . . . . 18 1.4 Concurrent vs Sequential Statements . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4.1 Concurrent Assignment vs Process . . . . . . . . . . . . . . . . . . . . . . 18 1.4.2 Conditional Assignment vs If Statements . . . . . . . . . . . . . . . . . . 18 1.4.3 Selected Assignment vs Case Statement . . . . . . . . . . . . . . . . . . . 19 1.4.4 Coding Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5 Overview of Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.1 Combinational Process vs Clocked Process . . . . . . . . . . . . . . . . . 22 1.5.2 Latch Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 i
4.
ii
CONTENTS 1.5.3 Combinational vs Flopped Signals . . . . . . . . . . . . . . . . . . . . . . 25 1.6 Details of Process Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6.1 Simple Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6.2 Temporal Granularities of Simulation . . . . . . . . . . . . . . . . . . . . 26 1.6.3 Intuition Behind Delta-Cycle Simulation . . . . . . . . . . . . . . . . . . 27 1.6.4 Definitions and Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6.4.1 Process Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6.4.2 Simulation Algorithm . . . . . . . . . . . . . . . . . . . . . . . 28 1.6.4.3 Delta-Cycle Definitions . . . . . . . . . . . . . . . . . . . . . . 30 1.6.5 Example 1: Process Execution (Bamboozle) . . . . . . . . . . . . . . . . . 31 1.6.6 Example 2: Process Execution (Flummox) . . . . . . . . . . . . . . . . . 40 1.6.7 Example: Need for Provisional Assignments . . . . . . . . . . . . . . . . 42 1.6.8 Delta-Cycle Simulations of Flip-Flops . . . . . . . . . . . . . . . . . . . . 44 1.7 Register-Transfer-Level Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1.7.2 Technique for Register-Transfer Level Simulation . . . . . . . . . . . . . . 52 1.7.3 Examples of RTL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 53 1.7.3.1 RTL Simulation Example 1 . . . . . . . . . . . . . . . . . . . . 53 1.8 VHDL and Hardware Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . 58 1.8.1 Basic Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 1.8.2 Deprecated Building Blocks for RTL . . . . . . . . . . . . . . . . . . . . 59 1.8.2.1 An Aside on Flip-Flops and Latches . . . . . . . . . . . . . . . 59 1.8.2.2 Deprecated Hardware . . . . . . . . . . . . . . . . . . . . . . . 59 1.8.3 Hardware and Code for Flops . . . . . . . . . . . . . . . . . . . . . . . . 60 1.8.3.1 Flops with Waits and Ifs . . . . . . . . . . . . . . . . . . . . . . 60 1.8.3.2 Flops with Synchronous Reset . . . . . . . . . . . . . . . . . . 60 1.8.3.3 Flops with Chip-Enable . . . . . . . . . . . . . . . . . . . . . . 61 1.8.3.4 Flop with Chip-Enable and Mux on Input . . . . . . . . . . . . . 61 1.8.3.5 Flops with Chip-Enable, Muxes, and Reset . . . . . . . . . . . . 62 1.8.4 An Example Sequential Circuit . . . . . . . . . . . . . . . . . . . . . . . 62 1.9 Arrays and Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.10 Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.10.1 Arithmetic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.10.2 Shift and Rotate Operations . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.10.3 Overloading of Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.10.4 Different Widths and Arithmetic . . . . . . . . . . . . . . . . . . . . . . . 69 1.10.5 Overloading of Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.10.6 Different Widths and Comparisons . . . . . . . . . . . . . . . . . . . . . . 69 1.10.7 Type Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 1.11 Synthesizable vs Non-Synthesizable Code . . . . . . . . . . . . . . . . . . . . . . 71 1.11.1 Unsynthesizable Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.11.1.1 Initial Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.11.1.2 Wait For . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.11.1.3 Different Wait Conditions . . . . . . . . . . . . . . . . . . . . . 72 1.11.1.4 Multiple “if rising edge” in Process . . . . . . . . . . . . . . . . 73
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iii 1.11.1.5 “if rising edge” and “wait” in Same Process . . . . . . . . . . . 73 1.11.1.6 “if rising edge” with “else” Clause . . . . . . . . . . . . . . . . 74 1.11.1.7 “if rising edge” Inside a “for” Loop . . . . . . . . . . . . . . . . 74 1.11.1.8 “wait” Inside of a “for loop” . . . . . . . . . . . . . . . . . . . 75 1.11.2 Synthesizable, but Bad Coding Practices . . . . . . . . . . . . . . . . . . . 76 1.11.2.1 Asynchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . 76 1.11.2.2 Combinational “if-then” Without “else” . . . . . . . . . . . . . 77 1.11.2.3 Bad Form of Nested Ifs . . . . . . . . . . . . . . . . . . . . . . 77 1.11.2.4 Deeply Nested Ifs . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.11.3 Synthesizable, but Unpredictable Hardware . . . . . . . . . . . . . . . . . 78 1.12 Synthesizable VHDL Coding Guidelines . . . . . . . . . . . . . . . . . . . . . . . 78 1.12.1 Signal Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 1.12.2 Flip-Flops and Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 1.12.3 Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 1.12.4 Multiplexors and Tri-State Signals . . . . . . . . . . . . . . . . . . . . . . 79 1.12.5 Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 1.12.6 State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 1.12.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 1.13 VHDL Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 P1.1 IEEE 1164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 P1.2 VHDL Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 P1.3 Flops, Latches, and Combinational Circuitry . . . . . . . . . . . . . . . . 85 P1.4 Counting Clock Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 P1.5 Arithmetic Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 P1.6 Delta-Cycle Simulation: Pong . . . . . . . . . . . . . . . . . . . . . . . . 89 P1.7 Delta-Cycle Simulation: Baku . . . . . . . . . . . . . . . . . . . . . . . . 89 P1.8 Clock-Cycle Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 P1.9 VHDL — VHDL Behavioural Comparison: Teradactyl . . . . . . . . . . . 92 P1.10 VHDL — VHDL Behavioural Comparison: Ichtyostega . . . . . . . . . . 93 P1.11 Waveform — VHDL Behavioural Comparison . . . . . . . . . . . . . . . 95 P1.12 Hardware — VHDL Comparison . . . . . . . . . . . . . . . . . . . . . . 97 P1.13 8-Bit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 P1.13.1 Asynchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . 98 P1.13.2 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 P1.13.3 Testbench for Register . . . . . . . . . . . . . . . . . . . . . . . 98 P1.14 Synthesizable VHDL and Hardware . . . . . . . . . . . . . . . . . . . . . 99 P1.15 Datapath Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 P1.15.1 Correct Implementation? . . . . . . . . . . . . . . . . . . . . . 101 P1.15.2 Smallest Area . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 P1.15.3 Shortest Clock Period . . . . . . . . . . . . . . . . . . . . . . . 104
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CONTENTS 2 RTL Design with VHDL 105 2.1 Prelude to Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.1.1 A Note on EDA for FPGAs and ASICs . . . . . . . . . . . . . . . . . . . 105 2.2 FPGA Background and Coding Guidelines . . . . . . . . . . . . . . . . . . . . . . 106 2.2.1 Generic FPGA Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.2.1.1 Generic FPGA Cell . . . . . . . . . . . . . . . . . . . . . . . . 106 2.2.2 Area Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.2.2.1 Interconnect for Generic FPGA . . . . . . . . . . . . . . . . . . 112 2.2.2.2 Blocks of Cells for Generic FPGA . . . . . . . . . . . . . . . . 112 2.2.2.3 Clocks for Generic FPGAs . . . . . . . . . . . . . . . . . . . . 114 2.2.2.4 Special Circuitry in FPGAs . . . . . . . . . . . . . . . . . . . . 114 2.2.3 Generic-FPGA Coding Guidelines . . . . . . . . . . . . . . . . . . . . . . 115 2.3 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2.3.1 Generic Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2.3.2 Implementation Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 2.3.3 Design Flow: Datapath vs Control vs Storage . . . . . . . . . . . . . . . . 118 2.3.3.1 Classes of Hardware . . . . . . . . . . . . . . . . . . . . . . . . 118 2.3.3.2 Datapath-Centric Design Flow . . . . . . . . . . . . . . . . . . 119 2.3.3.3 Control-Centric Design Flow . . . . . . . . . . . . . . . . . . . 120 2.3.3.4 Storage-Centric Design Flow . . . . . . . . . . . . . . . . . . . 120 2.4 Algorithms and High-Level Models . . . . . . . . . . . . . . . . . . . . . . . . . 120 2.4.1 Flow Charts and State Machines . . . . . . . . . . . . . . . . . . . . . . . 121 2.4.2 Data-Dependency Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . 121 2.4.3 High-Level Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 2.5 Finite State Machines in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 2.5.1 Introduction to State-Machine Design . . . . . . . . . . . . . . . . . . . . 123 2.5.1.1 Mealy vs Moore State Machines . . . . . . . . . . . . . . . . . 123 2.5.1.2 Introduction to State Machines and VHDL . . . . . . . . . . . . 123 2.5.1.3 Explicit vs Implicit State Machines . . . . . . . . . . . . . . . . 124 2.5.2 Implementing a Simple Moore Machine . . . . . . . . . . . . . . . . . . . 125 2.5.2.1 Implicit Moore State Machine . . . . . . . . . . . . . . . . . . . 126 2.5.2.2 Explicit Moore with Flopped Output . . . . . . . . . . . . . . . 127 2.5.2.3 Explicit Moore with Combinational Outputs . . . . . . . . . . . 128 2.5.2.4 Explicit-Current+Next Moore with Concurrent Assignment . . . 129 2.5.2.5 Explicit-Current+Next Moore with Combinational Process . . . 130 2.5.3 Implementing a Simple Mealy Machine . . . . . . . . . . . . . . . . . . . 131 2.5.3.1 Implicit Mealy State Machine . . . . . . . . . . . . . . . . . . . 132 2.5.3.2 Explicit Mealy State Machine . . . . . . . . . . . . . . . . . . . 133 2.5.3.3 Explicit-Current+Next Mealy . . . . . . . . . . . . . . . . . . . 134 2.5.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 2.5.5 State Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 2.5.5.1 Constants vs Enumerated Type . . . . . . . . . . . . . . . . . . 137 2.5.5.2 Encoding Schemes . . . . . . . . . . . . . . . . . . . . . . . . . 138 2.6 Dataflow Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 2.6.1 Dataflow Diagrams Overview . . . . . . . . . . . . . . . . . . . . . . . . 139
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v 2.6.2 Dataflow Diagrams, Hardware, and Behaviour . . . . . . . . . . . . . . . 142 2.6.3 Dataflow Diagram Execution . . . . . . . . . . . . . . . . . . . . . . . . . 143 2.6.4 Performance Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 2.6.5 Area Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 2.6.6 Design Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 2.6.7 Area / Performance Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . 145 2.7 Design Example: Massey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 2.7.1 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 2.7.2 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 2.7.3 Initial Dataflow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 2.7.4 Dataflow Diagram Scheduling . . . . . . . . . . . . . . . . . . . . . . . . 150 2.7.5 Optimize Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 152 2.7.6 Input/Output Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 2.7.7 Register Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 2.7.8 Datapath Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 2.7.9 Datapath for DP+Ctrl Model . . . . . . . . . . . . . . . . . . . . . . . . . 158 2.7.10 Peephole Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 2.8 Design Example: Vanier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 2.8.1 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 2.8.2 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 2.8.3 Initial Dataflow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 2.8.4 Reschedule to Meet Requirements . . . . . . . . . . . . . . . . . . . . . . 164 2.8.5 Optimize Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 2.8.6 Assign Names to Registered Values . . . . . . . . . . . . . . . . . . . . . 167 2.8.7 Input/Output Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 2.8.8 Tangent: Combinational Outputs . . . . . . . . . . . . . . . . . . . . . . . 170 2.8.9 Register Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 2.8.10 Datapath Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 2.8.11 Hardware Block Diagram and State Machine . . . . . . . . . . . . . . . . 173 2.8.11.1 Control for Registers . . . . . . . . . . . . . . . . . . . . . . . 173 2.8.11.2 Control for Datapath Components . . . . . . . . . . . . . . . . . 174 2.8.11.3 Control for State . . . . . . . . . . . . . . . . . . . . . . . . . . 175 2.8.11.4 Complete State Machine Table . . . . . . . . . . . . . . . . . . 175 2.8.12 VHDL Code with Explicit State Machine . . . . . . . . . . . . . . . . . . 176 2.8.13 Peephole Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 2.8.14 Notes and Observations . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 2.9 Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 2.9.1 Introduction to Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . 183 2.9.2 Partially Pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 2.9.3 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 2.10 Design Example: Pipelined Massey . . . . . . . . . . . . . . . . . . . . . . . . . 188 2.11 Memory Arrays and RTL Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 2.11.1 Memory Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 2.11.2 Memory Arrays in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . 193 2.11.2.1 Using a Two-Dimensional Array for Memory . . . . . . . . . . 193
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CONTENTS 2.11.2.2 Memory Arrays in Hardware . . . . . . . . . . . . . . . . . . . 194 2.11.2.3 VHDL Code for Single-Port Memory Array . . . . . . . . . . . 195 2.11.2.4 Using Library Components for Memory . . . . . . . . . . . . . 196 2.11.2.5 Build Memory from Slices . . . . . . . . . . . . . . . . . . . . 197 2.11.2.6 Dual-Ported Memory . . . . . . . . . . . . . . . . . . . . . . . 199 2.11.3 Data Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 2.11.4 Memory Arrays and Dataflow Diagrams . . . . . . . . . . . . . . . . . . . 201 2.11.5 Example: Memory Array and Dataflow Diagram . . . . . . . . . . . . . . 204 2.12 Input / Output Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 2.13 Example: Moving Average . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 2.13.1 Requirements and Environmental Assumptions . . . . . . . . . . . . . . . 207 2.13.2 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 2.13.3 Pseudocode and Dataflow Diagrams . . . . . . . . . . . . . . . . . . . . . 210 2.13.4 Control Tables and State Machine . . . . . . . . . . . . . . . . . . . . . . 216 2.13.5 VHDL Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 2.14 Design Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 P2.1 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 P2.1.1 Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . 221 P2.1.2 Own Code vs Libraries . . . . . . . . . . . . . . . . . . . . . . 221 P2.2 Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 P2.3 Dataflow Diagram Optimization . . . . . . . . . . . . . . . . . . . . . . . 222 P2.3.1 Resource Usage . . . . . . . . . . . . . . . . . . . . . . . . . . 222 P2.3.2 Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 P2.4 Dataflow Diagram Design . . . . . . . . . . . . . . . . . . . . . . . . . . 223 P2.4.1 Maximum Performance . . . . . . . . . . . . . . . . . . . . . . 223 P2.4.2 Minimum area . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 P2.5 Michener: Design and Optimization . . . . . . . . . . . . . . . . . . . . . 224 P2.6 Dataflow Diagrams with Memory Arrays . . . . . . . . . . . . . . . . . . 224 P2.6.1 Algorithm 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 P2.6.2 Algorithm 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 P2.7 2-bit adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 P2.7.1 Generic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 P2.7.2 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 P2.8 Sketches of Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
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vii 3 Performance Analysis and Optimization 227 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 3.2 Defining Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 3.3 Comparing Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 3.3.1 General Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 3.3.2 Example: Performance of Printers . . . . . . . . . . . . . . . . . . . . . . 229 3.4 Clock Speed, CPI, Program Length, and Performance . . . . . . . . . . . . . . . . 233 3.4.1 Mathematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 3.4.2 Example: CISC vs RISC and CPI . . . . . . . . . . . . . . . . . . . . . . 233 3.4.3 Effect of Instruction Set on Performance . . . . . . . . . . . . . . . . . . . 235 3.4.4 Effect of Time to Market on Relative Performance . . . . . . . . . . . . . 237 3.4.5 Summary of Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 3.5 Performance Analysis and Dataflow Diagrams . . . . . . . . . . . . . . . . . . . . 239 3.5.1 Dataflow Diagrams, CPI, and Clock Speed . . . . . . . . . . . . . . . . . 239 3.5.2 Examples of Dataflow Diagrams for Two Instructions . . . . . . . . . . . . 240 3.5.2.1 Scheduling of Operations for Different Clock Periods . . . . . . 241 3.5.2.2 Performance Computation for Different Clock Periods . . . . . . 241 3.5.2.3 Example: Two Instructions Taking Similar Time . . . . . . . . . 242 3.5.2.4 Example: Same Total Time, Different Order for A . . . . . . . . 243 3.5.3 Example: From Algorithm to Optimized Dataflow . . . . . . . . . . . . . 244 3.6 General Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 3.6.1 Strength Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 3.6.1.1 Arithmetic Strength Reduction . . . . . . . . . . . . . . . . . . 252 3.6.1.2 Boolean Strength Reduction . . . . . . . . . . . . . . . . . . . . 252 3.6.2 Replication and Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 3.6.2.1 Mux-Pushing . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 3.6.2.2 Common Subexpression Elimination . . . . . . . . . . . . . . . 253 3.6.2.3 Computation Replication . . . . . . . . . . . . . . . . . . . . . 253 3.6.3 Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 3.7 Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 3.8 Performance Analysis and Optimization Problems . . . . . . . . . . . . . . . . . . 256 P3.1 Farmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 P3.2 Network and Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 P3.2.1 Maximum Throughput . . . . . . . . . . . . . . . . . . . . . . . 257 P3.2.2 Packet Size and Performance . . . . . . . . . . . . . . . . . . . 257 P3.3 Performance Short Answer . . . . . . . . . . . . . . . . . . . . . . . . . . 257 P3.4 Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 P3.4.1 Average CPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 P3.4.2 Why not you too? . . . . . . . . . . . . . . . . . . . . . . . . . 258 P3.4.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 P3.5 Dataflow Diagram Optimization . . . . . . . . . . . . . . . . . . . . . . . 258 P3.6 Performance Optimization with Memory Arrays . . . . . . . . . . . . . . 259 P3.7 Multiply Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 P3.7.1 Highest Performance . . . . . . . . . . . . . . . . . . . . . . . 260 P3.7.2 Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . 261
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CONTENTS 4 Functional Verification 263 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 4.1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 4.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 4.2.1 Terminology: Validation / Verification / Testing . . . . . . . . . . . . . . . 264 4.2.2 The Difficulty of Designing Correct Chips . . . . . . . . . . . . . . . . . . 265 4.2.2.1 Notes from Kenn Heinrich (UW E&CE grad) . . . . . . . . . . 265 4.2.2.2 Notes from Aart de Geus (Chairman and CEO of Synopsys) . . . 265 4.3 Test Cases and Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 4.3.1 Test Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 4.3.2 Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 4.3.3 Floating Point Divider Example . . . . . . . . . . . . . . . . . . . . . . . 268 4.4 Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 4.4.1 Overview of Test Benches . . . . . . . . . . . . . . . . . . . . . . . . . . 271 4.4.2 Reference Model Style Testbench . . . . . . . . . . . . . . . . . . . . . . 272 4.4.3 Relational Style Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . 272 4.4.4 Coding Structure of a Testbench . . . . . . . . . . . . . . . . . . . . . . . 273 4.4.5 Datapath vs Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 4.4.6 Verification Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 4.5 Functional Verification for Datapath Circuits . . . . . . . . . . . . . . . . . . . . . 274 4.5.1 A Spec-Less Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 4.5.2 Use an Array for Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . 276 4.5.3 Build Spec into Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 4.5.4 Have Separate Specification Entity . . . . . . . . . . . . . . . . . . . . . . 278 4.5.5 Generate Test Vectors Automatically . . . . . . . . . . . . . . . . . . . . . 280 4.5.6 Relational Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 4.6 Functional Verification of Control Circuits . . . . . . . . . . . . . . . . . . . . . . 281 4.6.1 Overview of Queues in Hardware . . . . . . . . . . . . . . . . . . . . . . 281 4.6.2 VHDL Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 4.6.2.1 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 4.6.2.2 Other VHDL Coding . . . . . . . . . . . . . . . . . . . . . . . 283 4.6.3 Code Structure for Verification . . . . . . . . . . . . . . . . . . . . . . . . 283 4.6.4 Instrumentation Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 4.6.5 Coverage Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 4.6.6 Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 4.6.7 VHDL Coding Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 4.6.8 Queue Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 4.6.9 Queue Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 4.7 Example: Microwave Oven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 4.8 Functional Verification Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 P4.1 Carry Save Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 P4.2 Traffic Light Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 P4.2.1 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 P4.2.2 Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . 296 P4.2.3 Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
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ix P4.3 State Machines and Verification . . . . . . . . . . . . . . . . . . . . . . . 297 P4.3.1 Three Different State Machines . . . . . . . . . . . . . . . . . . 297 P4.3.2 State Machines in General . . . . . . . . . . . . . . . . . . . . . 298 P4.4 Test Plan Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 P4.4.1 Early Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 P4.4.2 Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 P4.5 Sketches of Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 5 Timing Analysis 301 5.1 Delays and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 5.1.1 Background Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 5.1.2 Clock-Related Timing Definitions . . . . . . . . . . . . . . . . . . . . . . 302 5.1.2.1 Clock Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 5.1.2.2 Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 5.1.2.3 Clock Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 5.1.3 Storage-Related Timing Definitions . . . . . . . . . . . . . . . . . . . . . 304 5.1.3.1 Flops and Latches . . . . . . . . . . . . . . . . . . . . . . . . . 304 5.1.3.2 Timing Parameters for a Flop . . . . . . . . . . . . . . . . . . . 305 5.1.3.3 Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 5.1.3.4 Clock-to-Q Time . . . . . . . . . . . . . . . . . . . . . . . . . . 305 5.1.4 Propagation Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 5.1.4.1 Load Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 5.1.4.2 Interconnect Delays . . . . . . . . . . . . . . . . . . . . . . . . 306 5.1.5 Summary of Delay Factors . . . . . . . . . . . . . . . . . . . . . . . . . . 307 5.1.6 Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 5.1.6.1 Minimum Clock Period . . . . . . . . . . . . . . . . . . . . . . 308 5.1.6.2 Hold Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . 309 5.1.6.3 Example Timing Violations . . . . . . . . . . . . . . . . . . . . 309 5.2 Timing Analysis of Latches and Flip Flops . . . . . . . . . . . . . . . . . . . . . . 311 5.2.1 Simple Multiplexer Latch . . . . . . . . . . . . . . . . . . . . . . . . . . 311 5.2.1.1 Structure and Behaviour of Multiplexer Latch . . . . . . . . . . 311 5.2.1.2 Strategy for Timing Analysis of Storage Devices . . . . . . . . . 313 5.2.1.3 Clock-to-Q Time of a Multiplexer Latch . . . . . . . . . . . . . 314 5.2.1.4 Setup Timing of a Multiplexer Latch . . . . . . . . . . . . . . . 315 5.2.1.5 Hold Time of a Multiplexer Latch . . . . . . . . . . . . . . . . . 323 5.2.1.6 Example of a Bad Latch . . . . . . . . . . . . . . . . . . . . . . 326 5.2.2 Timing Analysis of Transmission-Gate Latch . . . . . . . . . . . . . . . . 326 5.2.2.1 Structure and Behaviour of a Transmission Gate . . . . . . . . . 327 5.2.2.2 Structure and Behaviour of Transmission-Gate Latch . . . . . . 327 5.2.2.3 Clock-to-Q Delay for Transmission-Gate Latch . . . . . . . . . 328 5.2.2.4 Setup and Hold Times for Transmission-Gate Latch . . . . . . . 328 5.2.3 Falling Edge Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 5.2.3.1 Structure and Behaviour of Flip-Flop . . . . . . . . . . . . . . . 329 5.2.3.2 Clock-to-Q of Flip-Flop . . . . . . . . . . . . . . . . . . . . . . 330 5.2.3.3 Setup of Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . 331
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CONTENTS 5.2.3.4 Hold of Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . 332 5.2.4 Timing Analysis of FPGA Cells . . . . . . . . . . . . . . . . . . . . . . . 332 5.2.4.1 Standard Timing Equations . . . . . . . . . . . . . . . . . . . . 333 5.2.4.2 Hierarchical Timing Equations . . . . . . . . . . . . . . . . . . 333 5.2.4.3 Actel Act 2 Logic Cell . . . . . . . . . . . . . . . . . . . . . . . 333 5.2.4.4 Timing Analysis of Actel Sequential Module . . . . . . . . . . . 335 5.2.5 Exotic Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 5.3 Critical Paths and False Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 5.3.1 Introduction to Critical and False Paths . . . . . . . . . . . . . . . . . . . 336 5.3.1.1 Example of Critical Path in Full Adder . . . . . . . . . . . . . . 338 5.3.1.2 Preliminaries for Critical Paths . . . . . . . . . . . . . . . . . . 340 5.3.1.3 Longest Path and Critical Path . . . . . . . . . . . . . . . . . . 340 5.3.1.4 Timing Simulation vs Static Timing Analysis . . . . . . . . . . . 343 5.3.2 Longest Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 5.3.3 Detecting a False Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 5.3.3.1 Preliminaries for Detecting a False Path . . . . . . . . . . . . . 345 5.3.3.2 Almost-Correct Algorithm to Detect a False Path . . . . . . . . . 349 5.3.3.3 Examples of Detecting False Paths . . . . . . . . . . . . . . . . 349 5.3.4 Finding the Next Candidate Path . . . . . . . . . . . . . . . . . . . . . . . 354 5.3.4.1 Algorithm to Find Next Candidate Path . . . . . . . . . . . . . . 354 5.3.4.2 Examples of Finding Next Candidate Path . . . . . . . . . . . . 355 5.3.5 Correct Algorithm to Find Critical Path . . . . . . . . . . . . . . . . . . . 362 5.3.5.1 Rules for Late Side Inputs . . . . . . . . . . . . . . . . . . . . . 362 5.3.5.2 Monotone Speedup . . . . . . . . . . . . . . . . . . . . . . . . 364 5.3.5.3 Analysis of Side-Input-Causes-Glitch Situation . . . . . . . . . 365 5.3.5.4 Complete Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 366 5.3.5.5 Complete Examples . . . . . . . . . . . . . . . . . . . . . . . . 367 5.3.6 Further Extensions to Critical Path Analysis . . . . . . . . . . . . . . . . . 374 5.3.7 Increasing the Accuracy of Critical Path Analysis . . . . . . . . . . . . . . 375 5.4 Elmore Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 5.4.1 RC-Networks for Timing Analysis . . . . . . . . . . . . . . . . . . . . . . 375 5.4.2 Derivation of Analog Timing Model . . . . . . . . . . . . . . . . . . . . . 380 5.4.2.1 Example Derivation: Equation for Voltage at Node 3 . . . . . . . 382 5.4.2.2 General Derivation . . . . . . . . . . . . . . . . . . . . . . . . . 383 5.4.3 Elmore Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 5.4.4 Examples of Using Elmore Delay . . . . . . . . . . . . . . . . . . . . . . 387 5.4.4.1 Interconnect with Single Fanout . . . . . . . . . . . . . . . . . . 387 5.4.4.2 Interconnect with Multiple Gates in Fanout . . . . . . . . . . . . 389 5.5 Practical Usage of Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 392 5.5.1 Speed Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 5.5.1.1 FPGAs, Interconnect, and Synthesis . . . . . . . . . . . . . . . 394 5.5.2 Worst Case Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 5.5.2.1 Fanout delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 5.5.2.2 Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . 394 5.6 Timing Analysis Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
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xi P5.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 P5.2 Hold Time Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 P5.2.1 Cause . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 P5.2.2 Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 P5.2.3 Rectification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 P5.3 Latch Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 P5.4 Critical Path and False Path . . . . . . . . . . . . . . . . . . . . . . . . . 398 P5.5 Critical Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 P5.5.1 Longest Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 P5.5.2 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 P5.5.3 Missing Factors . . . . . . . . . . . . . . . . . . . . . . . . . . 399 P5.5.4 Critical Path or False Path? . . . . . . . . . . . . . . . . . . . . 399 P5.6 YACP: Yet Another Critical Path . . . . . . . . . . . . . . . . . . . . . . . 400 P5.7 Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 P5.8 Short Answer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 P5.8.1 Wires in FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . 402 P5.8.2 Age and Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 P5.8.3 Temperature and Delay . . . . . . . . . . . . . . . . . . . . . . 402 P5.9 Worst Case Conditions and Derating Factor . . . . . . . . . . . . . . . . . 402 P5.9.1 Worst-Case Commercial . . . . . . . . . . . . . . . . . . . . . . 402 P5.9.2 Worst-Case Industrial . . . . . . . . . . . . . . . . . . . . . . . 402 P5.9.3 Worst-Case Industrial, Non-Ambient Junction Temperature . . . 402 6 Power Analysis and Power-Aware Design 403 6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 6.1.1 Importance of Power and Energy . . . . . . . . . . . . . . . . . . . . . . . 403 6.1.2 Industrial Names and Products . . . . . . . . . . . . . . . . . . . . . . . . 403 6.1.3 Power vs Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 6.1.4 Batteries, Power and Energy . . . . . . . . . . . . . . . . . . . . . . . . . 405 6.1.4.1 Do Batteries Store Energy or Power? . . . . . . . . . . . . . . . 405 6.1.4.2 Battery Life and Efficiency . . . . . . . . . . . . . . . . . . . . 405 6.1.4.3 Battery Life and Power . . . . . . . . . . . . . . . . . . . . . . 406 6.2 Power Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 6.2.1 Switching Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 6.2.2 Short-Circuited Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 6.2.3 Leakage Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 6.2.4 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 6.2.5 Note on Power Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 6.3 Overview of Power Reduction Techniques . . . . . . . . . . . . . . . . . . . . . . 414 6.4 Voltage Reduction for Power Reduction . . . . . . . . . . . . . . . . . . . . . . . 415 6.5 Data Encoding for Power Reduction . . . . . . . . . . . . . . . . . . . . . . . . . 416 6.5.1 How Data Encoding Can Reduce Power . . . . . . . . . . . . . . . . . . . 416 6.5.2 Example Problem: Sixteen Pulser . . . . . . . . . . . . . . . . . . . . . . 419 6.5.2.1 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . 419 6.5.2.2 Additional Information . . . . . . . . . . . . . . . . . . . . . . 420
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CONTENTS 6.5.2.3 Answer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 6.6 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 6.6.1 Introduction to Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . 424 6.6.2 Implementing Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . 425 6.6.3 Design Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 6.6.4 Effectiveness of Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . 427 6.6.5 Example: Reduced Activity Factor with Clock Gating . . . . . . . . . . . 429 6.6.6 Clock Gating with Valid-Bit Protocol . . . . . . . . . . . . . . . . . . . . 431 6.6.6.1 Valid-Bit Protocol . . . . . . . . . . . . . . . . . . . . . . . . . 431 6.6.6.2 How Many Clock Cycles for Module? . . . . . . . . . . . . . . 433 6.6.6.3 Adding Clock-Gating Circuitry . . . . . . . . . . . . . . . . . . 434 6.6.7 Example: Pipelined Circuit with Clock-Gating . . . . . . . . . . . . . . . 437 6.7 Power Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 P6.1 Short Answers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 P6.1.1 Power and Temperature . . . . . . . . . . . . . . . . . . . . . . 439 P6.1.2 Leakage Power . . . . . . . . . . . . . . . . . . . . . . . . . . 439 P6.1.3 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 P6.1.4 Gray Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 P6.2 VLSI Gurus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 P6.2.1 Effect on Power . . . . . . . . . . . . . . . . . . . . . . . . . . 439 P6.2.2 Critique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 P6.3 Advertising Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 P6.4 Vary Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 P6.5 Clock Speed Increase Without Power Increase . . . . . . . . . . . . . . . 441 P6.5.1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 P6.5.2 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 P6.6 Power Reduction Strategies . . . . . . . . . . . . . . . . . . . . . . . . . 441 P6.6.1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 P6.6.2 Transistor Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . 441 P6.6.3 Adding Registers to Inputs . . . . . . . . . . . . . . . . . . . . 441 P6.6.4 Gray Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 P6.7 Power Consumption on New Chip . . . . . . . . . . . . . . . . . . . . . . 442 P6.7.1 Hypothesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 P6.7.2 Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 P6.7.3 Reality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
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xiii 7 Fault Testing and Testability 443 7.1 Faults and Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 7.1.1 Overview of Faults and Testing . . . . . . . . . . . . . . . . . . . . . . . 443 7.1.1.1 Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 7.1.1.2 Causes of Faults . . . . . . . . . . . . . . . . . . . . . . . . . . 443 7.1.1.3 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 7.1.1.4 Burn In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 7.1.1.5 Bin Sorting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 7.1.1.6 Testing Techniques . . . . . . . . . . . . . . . . . . . . . . . . 445 7.1.1.7 Design for Testability (DFT) . . . . . . . . . . . . . . . . . . . 445 7.1.2 Example Problem: Economics of Testing . . . . . . . . . . . . . . . . . . 446 7.1.3 Physical Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 7.1.3.1 Types of Physical Faults . . . . . . . . . . . . . . . . . . . . . . 447 7.1.3.2 Locations of Faults . . . . . . . . . . . . . . . . . . . . . . . . 447 7.1.3.3 Layout Affects Locations . . . . . . . . . . . . . . . . . . . . . 448 7.1.3.4 Naming Fault Locations . . . . . . . . . . . . . . . . . . . . . . 448 7.1.4 Detecting a Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 7.1.4.1 Which Test Vectors will Detect a Fault? . . . . . . . . . . . . . 449 7.1.5 Mathematical Models of Faults . . . . . . . . . . . . . . . . . . . . . . . 450 7.1.5.1 Single Stuck-At Fault Model . . . . . . . . . . . . . . . . . . . 450 7.1.6 Generate Test Vector to Find a Mathematical Fault . . . . . . . . . . . . . 451 7.1.6.1 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 7.1.6.2 Example of Finding a Test Vector . . . . . . . . . . . . . . . . . 452 7.1.7 Undetectable Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 7.1.7.1 Redundant Circuitry . . . . . . . . . . . . . . . . . . . . . . . . 452 7.1.7.2 Curious Circuitry and Fault Detection . . . . . . . . . . . . . . 454 7.2 Test Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 7.2.1 A Small Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 7.2.2 Choosing Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 7.2.2.1 Fault Domination . . . . . . . . . . . . . . . . . . . . . . . . . 456 7.2.2.2 Fault Equivalence . . . . . . . . . . . . . . . . . . . . . . . . . 457 7.2.2.3 Gate Collapsing . . . . . . . . . . . . . . . . . . . . . . . . . . 457 7.2.2.4 Node Collapsing . . . . . . . . . . . . . . . . . . . . . . . . . . 458 7.2.2.5 Fault Collapsing Summary . . . . . . . . . . . . . . . . . . . . 458 7.2.3 Fault Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 7.2.4 Test Vector Generation and Fault Detection . . . . . . . . . . . . . . . . . 459 7.2.5 Generate Test Vectors for 100% Coverage . . . . . . . . . . . . . . . . . . 459 7.2.5.1 Collapse the Faults . . . . . . . . . . . . . . . . . . . . . . . . 460 7.2.5.2 Check for Fault Domination . . . . . . . . . . . . . . . . . . . . 462 7.2.5.3 Required Test Vectors . . . . . . . . . . . . . . . . . . . . . . . 463 7.2.5.4 Faults Not Covered by Required Test Vectors . . . . . . . . . . . 463 7.2.5.5 Order to Run Test Vectors . . . . . . . . . . . . . . . . . . . . . 464 7.2.5.6 Summary of Technique to Find and Order Test Vectors . . . . . 465 7.2.5.7 Complete Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 466 7.2.6 One Fault Hiding Another . . . . . . . . . . . . . . . . . . . . . . . . . . 467
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CONTENTS 7.3 Scan Testing in General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 7.3.1 Structure and Behaviour of Scan Testing . . . . . . . . . . . . . . . . . . . 468 7.3.2 Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 7.3.2.1 Circuitry in Normal and Scan Mode . . . . . . . . . . . . . . . 468 7.3.2.2 Scan in Operation . . . . . . . . . . . . . . . . . . . . . . . . . 469 7.3.2.3 Scan in Operation with Example Circuit . . . . . . . . . . . . . 470 7.3.3 Summary of Scan Testing . . . . . . . . . . . . . . . . . . . . . . . . . . 475 7.3.4 Time to Test a Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 7.3.4.1 Example: Time to Test a Chip . . . . . . . . . . . . . . . . . . . 476 7.4 Boundary Scan and JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 7.4.1 Boundary Scan History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 7.4.2 JTAG Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 7.4.3 Scan Registers and Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 7.4.4 Scan Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 7.4.5 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 7.4.6 Other descriptions of JTAG/IEEE 1194.1 . . . . . . . . . . . . . . . . . . 480 7.5 Built In Self Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 7.5.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 7.5.1.1 Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 7.5.1.2 Linear Feedback Shift Register (LFSR) . . . . . . . . . . . . . . 483 7.5.1.3 Maximal-Length LFSR . . . . . . . . . . . . . . . . . . . . . . 484 7.5.2 Test Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 7.5.3 Signature Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 7.5.4 Result Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 7.5.5 Arithmetic over Binary Fields . . . . . . . . . . . . . . . . . . . . . . . . 487 7.5.6 Shift Registers and Characteristic Polynomials . . . . . . . . . . . . . . . 487 7.5.6.1 Circuit Multiplication . . . . . . . . . . . . . . . . . . . . . . . 489 7.5.7 Bit Streams and Characteristic Polynomials . . . . . . . . . . . . . . . . . 489 7.5.8 Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 7.5.9 Signature Analysis: Math and Circuits . . . . . . . . . . . . . . . . . . . . 490 7.5.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 7.6 Scan vs Self Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 7.7 Problems on Faults, Testing, and Testability . . . . . . . . . . . . . . . . . . . . . 497 P7.1 Based on Smith q14.9: Testing Cost . . . . . . . . . . . . . . . . . . . . . 497 P7.2 Testing Cost and Total Cost . . . . . . . . . . . . . . . . . . . . . . . . . 497 P7.3 Minimum Number of Faults . . . . . . . . . . . . . . . . . . . . . . . . . 498 P7.4 Smith q14.10: Fault Collapsing . . . . . . . . . . . . . . . . . . . . . . . 498 P7.5 Mathematical Models and Reality . . . . . . . . . . . . . . . . . . . . . . 498 P7.6 Undetectable Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 P7.7 Test Vector Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 P7.7.1 Choice of Test Vectors . . . . . . . . . . . . . . . . . . . . . . . 499 P7.7.2 Number of Test Vectors . . . . . . . . . . . . . . . . . . . . . . 499 P7.8 Time to do a Scan Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 P7.9 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 P7.9.1 Characteristic Polynomials . . . . . . . . . . . . . . . . . . . . 499
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xv P7.9.2 Test Generation . . . . . . . . . . . . . . . . . . . . . . . . . . 500 P7.9.3 Signature Analyzer . . . . . . . . . . . . . . . . . . . . . . . . 500 P7.9.4 Probabilty of Catching a Fault . . . . . . . . . . . . . . . . . . . 500 P7.9.5 Probabilty of Catching a Fault . . . . . . . . . . . . . . . . . . . 500 P7.9.6 Detecting a Specific Fault . . . . . . . . . . . . . . . . . . . . . 500 P7.9.7 Time to Run Test . . . . . . . . . . . . . . . . . . . . . . . . . 500 P7.10 Power and BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 P7.11 Timing Hazards and Testability . . . . . . . . . . . . . . . . . . . . . . . 501 P7.12 Testing Short Answer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 P7.12.1 Are there any physical faults that are detectable by scan testing but not by built-in self testing? . . . . . . . . . . . . . . . . . . 501 P7.12.2 Are there any physical faults that are detectable by built-in self testing but not by scan testing? . . . . . . . . . . . . . . . . . . 501 P7.13 Fault Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 P7.13.1 Design test generator . . . . . . . . . . . . . . . . . . . . . . . 502 P7.13.2 Design signature analyzer . . . . . . . . . . . . . . . . . . . . . 502 P7.13.3 Determine if a fault is detectable . . . . . . . . . . . . . . . . . 502 P7.13.4 Testing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 8 Review 503 8.1 Overview of the Term . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 8.2 VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 8.2.1 VHDL Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 8.2.2 VHDL Example Problems . . . . . . . . . . . . . . . . . . . . . . . . . . 504 8.3 RTL Design Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 8.3.1 Design Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 8.3.2 Design Example Problems . . . . . . . . . . . . . . . . . . . . . . . . . . 505 8.4 Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 8.4.1 Verification Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 8.4.2 Verification Example Problems . . . . . . . . . . . . . . . . . . . . . . . . 506 8.5 Performance Analysis and Optimization . . . . . . . . . . . . . . . . . . . . . . . 507 8.5.1 Performance Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 8.5.2 Performance Example Problems . . . . . . . . . . . . . . . . . . . . . . . 507 8.6 Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 8.6.1 Timing Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 8.6.2 Timing Example Problems . . . . . . . . . . . . . . . . . . . . . . . . . . 508 8.7 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 8.7.1 Power Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 8.7.2 Power Example Problems . . . . . . . . . . . . . . . . . . . . . . . . . . 509 8.8 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 8.8.1 Testing Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 8.8.2 Testing Example Problems . . . . . . . . . . . . . . . . . . . . . . . . . . 510 8.9 Formulas to be Given on Final Exam . . . . . . . . . . . . . . . . . . . . . . . . . 511
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CONTENTS II Solutions to Assignment Problems 1 1 VHDL Problems 3 P1.1 IEEE 1164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 P1.2 VHDL Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 P1.3 Flops, Latches, and Combinational Circuitry . . . . . . . . . . . . . . . . . . . . . 7 P1.4 Counting Clock Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 P1.5 Arithmetic Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 P1.6 Delta-Cycle Simulation: Pong . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 P1.7 Delta-Cycle Simulation: Baku . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 P1.8 Clock-Cycle Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 P1.9 VHDL — VHDL Behavioural Comparison: Teradactyl . . . . . . . . . . . . . . . 20 P1.10VHDL — VHDL Behavioural Comparison: Ichtyostega . . . . . . . . . . . . . . 21 P1.11Waveform — VHDL Behavioural Comparison . . . . . . . . . . . . . . . . . . . . 23 P1.12Hardware — VHDL Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 25 P1.138-Bit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 P1.13.1 Asynchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 P1.13.2 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 P1.13.3 Testbench for Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 P1.14Synthesizable VHDL and Hardware . . . . . . . . . . . . . . . . . . . . . . . . . 30 P1.15Datapath Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 P1.15.1 Correct Implementation? . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 P1.15.2 Smallest Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 P1.15.3 Shortest Clock Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2 Design Problems 39 P2.1 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 P2.1.1 Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 P2.1.2 Own Code vs Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 P2.2 Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 P2.3 Dataflow Diagram Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 P2.3.1 Resource Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 P2.3.2 Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 P2.4 Dataflow Diagram Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 P2.4.1 Maximum Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 P2.4.2 Minimum area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 P2.5 Michener: Design and Optimization . . . . . . . . . . . . . . . . . . . . . . . . . 47 P2.6 Dataflow Diagrams with Memory Arrays . . . . . . . . . . . . . . . . . . . . . . 48 P2.6.1 Algorithm 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 P2.6.2 Algorithm 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 P2.7 2-bit adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 P2.7.1 Generic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 P2.7.2 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 P2.8 Sketches of Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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xvii 3 Functional Verification Problems 55 P3.1 Carry Save Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 P3.2 Traffic Light Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 P3.2.1 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 P3.2.2 Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 P3.2.3 Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 P3.3 State Machines and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 P3.3.1 Three Different State Machines . . . . . . . . . . . . . . . . . . . . . . . 57 P3.3.1.1 Number of Test Scenarios . . . . . . . . . . . . . . . . . . . . . 57 P3.3.1.2 Length of Test Scenario . . . . . . . . . . . . . . . . . . . . . . 58 P3.3.1.3 Number of Flip Flops . . . . . . . . . . . . . . . . . . . . . . . 58 P3.3.2 State Machines in General . . . . . . . . . . . . . . . . . . . . . . . . . . 59 P3.4 Test Plan Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 P3.4.1 Early Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 P3.4.2 Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 P3.5 Sketches of Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4 Performance Analysis and Optimization Problems 63 P4.1 Farmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 P4.2 Network and Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 P4.2.1 Maximum Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 P4.2.2 Packet Size and Performance . . . . . . . . . . . . . . . . . . . . . . . . . 66 P4.3 Performance Short Answer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 P4.4 Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 P4.4.1 Average CPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 P4.4.2 Why not you too? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 P4.4.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 P4.5 Dataflow Diagram Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 P4.6 Performance Optimization with Memory Arrays . . . . . . . . . . . . . . . . . . . 70 P4.7 Multiply Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 P4.7.1 Highest Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 P4.7.2 Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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CONTENTS 5 Timing Analysis Problems 79 P5.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 P5.2 Hold Time Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 P5.2.1 Cause . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 P5.2.2 Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 P5.2.3 Rectification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 P5.3 Latch Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 P5.4 Critical Path and False Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 P5.5 Critical Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 P5.5.1 Longest Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 P5.5.2 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 P5.5.3 Missing Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 P5.5.4 Critical Path or False Path? . . . . . . . . . . . . . . . . . . . . . . . . . . 85 P5.6 YACP: Yet Another Critical Path . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 P5.7 Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 P5.8 Short Answer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 P5.8.1 Wires in FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 P5.8.2 Age and Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 P5.8.3 Temperature and Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 P5.9 Worst Case Conditions and Derating Factor . . . . . . . . . . . . . . . . . . . . . 90 P5.9.1 Worst-Case Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 P5.9.2 Worst-Case Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 P5.9.3 Worst-Case Industrial, Non-Ambient Junction Temperature . . . . . . . . . 90
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xix 6 Power Problems 91 P6.1 Short Answers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 P6.1.1 Power and Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 P6.1.2 Leakage Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 P6.1.3 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 P6.1.4 Gray Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 P6.2 VLSI Gurus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 P6.2.1 Effect on Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 P6.2.2 Critique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 P6.3 Advertising Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 P6.4 Vary Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 P6.5 Clock Speed Increase Without Power Increase . . . . . . . . . . . . . . . . . . . . 95 P6.5.1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 P6.5.2 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 P6.6 Power Reduction Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 P6.6.1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 P6.6.2 Transistor Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 P6.6.3 Adding Registers to Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 97 P6.6.4 Gray Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 P6.7 Power Consumption on New Chip . . . . . . . . . . . . . . . . . . . . . . . . . . 98 P6.7.1 Hypothesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 P6.7.2 Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 P6.7.3 Reality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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CONTENTS 7 Problems on Faults, Testing, and Testability 101 P7.1 Based on Smith q14.9: Testing Cost . . . . . . . . . . . . . . . . . . . . . . . . . 101 P7.2 Testing Cost and Total Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 P7.3 Minimum Number of Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 P7.4 Smith q14.10: Fault Collapsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 P7.5 Mathematical Models and Reality . . . . . . . . . . . . . . . . . . . . . . . . . . 105 P7.6 Undetectable Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 P7.7 Test Vector Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 P7.7.1 Choice of Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 P7.7.2 Number of Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 P7.8 Time to do a Scan Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 P7.9 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 P7.9.1 Characteristic Polynomials . . . . . . . . . . . . . . . . . . . . . . . . . . 107 P7.9.2 Test Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 P7.9.3 Signature Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 P7.9.4 Probabilty of Catching a Fault . . . . . . . . . . . . . . . . . . . . . . . . 113 P7.9.5 Probabilty of Catching a Fault . . . . . . . . . . . . . . . . . . . . . . . . 114 P7.9.6 Detecting a Specific Fault . . . . . . . . . . . . . . . . . . . . . . . . . . 114 P7.9.7 Time to Run Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 P7.10Power and BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 P7.11Timing Hazards and Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 P7.12Testing Short Answer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 P7.12.1 Are there any physical faults that are detectable by scan testing but not by built-in self testing? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 P7.12.2 Are there any physical faults that are detectable by built-in self testing but not by scan testing? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 P7.13Fault Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 P7.13.1 Design test generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 P7.13.2 Design signature analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . 119 P7.13.3 Determine if a fault is detectable . . . . . . . . . . . . . . . . . . . . . . . 120 P7.13.4 Testing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
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Part I Course Notes
1
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