7. Nyuzi Processor特色-SIMD
• A custom RISC instruction set (load-store architecture)
• 30 general purpose scalar registers
• 32 vector registers, each with 16 lanes
• Instructions are 32-bit fixed length and must be 32-bit aligned
des op2 op1 mask
add_i_mask v1, s2, v2, v3
total number of registers available per block: 65536
我比較大
需透過LLVM-
GPGPU來產
生machine
code
23. 參考SoCKit Video Server and Video IP (VIP) Reference Design設
LWAXI
F2H
使用Qsys連接AXI master/slave
24. Software IP使用Qsys,有這麼簡單@@?
• 必須了解AXI master slave
• AMBA AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite
• 我不了解,但我會改 Demo AXI Memory Design Example
• Qsys System Design Tutorial
• 注意細節:
• 所有AXI master或者slave的pin都要宣告
• AXI slave's ID bit width
• If an AXI slave's ID bit width is smaller than required for your system, the AXI slave response
might not reach all AXI
• maximum_master_id_width_in_the_interconnect +
log2(number_of_masters_in_the_same_interconnect)
• 所以我把Nyuzi Processor製作成Qsys元件