Please write out VHDL code by hand USING SELECTED SIGNAL METHOD!!! Thank you... Write a VHDL code using Selected Signal Assigment inside a process to design the following circuit: Solution entity example is Port ( X: in STD_LOGIC_VECTOR(3 DOWNTO 0); F: out STD_LOGIC); end example; architecture Behavioral of example is signal a,b: std_logic; begin process(X) begin a<= X(0) and (not x(1)); b<= X(2) and (not X(3)); Y<=not(a or b); end process; end Behavioral;.

1. Please write out VHDL code by hand USING SELECTED SIGNAL METHOD!!!
Thank you... Write a VHDL code using Selected Signal Assigment inside a process to design the
following circuit:
Solution
entity example is
Port ( X: in STD_LOGIC_VECTOR(3 DOWNTO 0);
F: out STD_LOGIC);
end example;
architecture Behavioral of example is
signal a,b: std_logic;
begin
process(X)
begin
a<= X(0) and (not x(1));
b<= X(2) and (not X(3));
Y<=not(a or b);
end process;
end Behavioral;