This document provides an outline for a course on programming the ARM microprocessor for embedded systems. It covers topics like ARM technology overview, tools and products, the ARM processor, instruction sets, exceptions and interrupts, firmware, operating systems, caches, and memory management. The goals are to develop an understanding of ARM execution required for embedded software development, with or without an operating system. Students should have prior knowledge of programming, operating systems, and embedded systems.

1. Programming the ARM
Microprocessor for Embedded
Systems
Ajay Dudani
Version 1.0

2. Copyrights
• This document is available under the
terms of Creative Commons Attribution-
NonCommercial-NoDerivs 2.5 License
• In simpler terms, you may
– Reproduce and redistribute this document as-
is for non-commercial use
Copyright (c) 2006 by Ajay Dudani 2
May not be reproduced or redistributed for commercial use.

3. Goals
• Develop a good understanding of
execution of ARM processor required to
develop and debug embedded software
with or without an operating system
• Students should have prior knowledge
about programming, operating system
concepts and understanding of embedded
systems
Copyright (c) 2006 by Ajay Dudani 3
May not be reproduced or redistributed for commercial use.

4. Outline
• ARM Technology Overview
• ARM Tools & Products
• ARM Processor
• ARM Toolchain
• ARM Instruction set
• Thumb instruction set
• ARM exception and interrupts
• ARM Firmware
• Embedded operating system
• ARM Caches
• Memory management and protection
• ARM Future development
Copyright (c) 2006 by Ajay Dudani 4
May not be reproduced or redistributed for commercial use.

5. Why ARM?
• Low power consumption
• Fast execution per Watt
• Good backward compatibility
• Inexpensive
• Variety of core offerings
• … and other advantages we will see in
upcoming slides
Copyright (c) 2006 by Ajay Dudani 5
May not be reproduced or redistributed for commercial use.

6. Why ARM?
• And …
Marketing 
Copyright (c) 2006 by Ajay Dudani 6
May not be reproduced or redistributed for commercial use.

7. Detailed Outline
• ARM Technology
– History
– The competition
Copyright (c) 2006 by Ajay Dudani 7
May not be reproduced or redistributed for commercial use.

8. Detailed Outline
• ARM Tools and products
– Microprocessors
– Compilers and debuggers
– Single board computers
– Documents and reference text
Copyright (c) 2006 by Ajay Dudani 8
May not be reproduced or redistributed for commercial use.

9. Detailed Outline
• ARM Processor
– Programming model
– General purpose registers
– Program control registers
– Pipelining
– Memory protection
Copyright (c) 2006 by Ajay Dudani 9
May not be reproduced or redistributed for commercial use.

10. Detailed Outline
• Toolchain
– ARM Toolchain
– GNU Toolchain
– Others
Copyright (c) 2006 by Ajay Dudani 10
May not be reproduced or redistributed for commercial use.

11. Detailed Outline
• ARM Instruction Set
– Instruction set encoding
– Conditional field
– Data processing instructions
– Branch instructions
– Load-store instructions
– Software interrupt instruction
– Program status register instructions
– Semaphore instructions
– Coprocessor instructions
– Extending instructions
Copyright (c) 2006 by Ajay Dudani 11
May not be reproduced or redistributed for commercial use.

12. Detailed Outline
• ARM Thumb Mode
– Why Thumb?
– Instruction set encoding
– Branch instructions
– Data processing instructions
– Load and store instructions
– Switching between ARM and Thumb mode
Copyright (c) 2006 by Ajay Dudani 12
May not be reproduced or redistributed for commercial use.

13. Detailed Outline
• ARM Exceptions and Interrupts
– Exception vector table
– Exception modes
– Exception and interrupt handling
Copyright (c) 2006 by Ajay Dudani 13
May not be reproduced or redistributed for commercial use.

14. Detailed Outline
• ARM Firmware
– Bootloader
– Standalone code
– Example of initialization
Copyright (c) 2006 by Ajay Dudani 14
May not be reproduced or redistributed for commercial use.

15. Detailed Outline
• ARM and Embedded OS
– Concepts of embedded OS
– Example of simple embedded OS
– Survey of embedded OS for ARM
Copyright (c) 2006 by Ajay Dudani 15
May not be reproduced or redistributed for commercial use.

16. Detailed Outline
• ARM Caches
– Memory hierarchy
– Cache policy
– Flushing policy
– Software performance
Copyright (c) 2006 by Ajay Dudani 16
May not be reproduced or redistributed for commercial use.

17. Detailed Outline
• ARM MMU and MPU
– Protected memory
– Example of memory protection
– Virtual memory concepts
– Example of virtual memory system
Copyright (c) 2006 by Ajay Dudani 17
May not be reproduced or redistributed for commercial use.

18. Outline
• ARM Technology Overview
• ARM Tools & Products
• ARM Processor
• ARM Toolchain
• ARM Instruction set
• Thumb instruction set
• ARM exception and interrupts
• ARM Firmware
• Embedded operating system
• ARM Caches
• Memory management and protection
• ARM Future development
Copyright (c) 2006 by Ajay Dudani 18
May not be reproduced or redistributed for commercial use.

19. ARM Technology Overview
• ARM: “The Architecture For The Digital
World”
• ARM is a physical hardware design and
intellectual property company
• ARM licenses its cores out and other
companies make processors based on its
cores
• ARM also provides toolchain and
debugging tools for its cores
Copyright (c) 2006 by Ajay Dudani 19
May not be reproduced or redistributed for commercial use.

20. ARM Technology Overview (2)
Companies licensing ARM IP:
Motorola
3Com
Panasonic
Agilent Technologies
Qualcomm
Altera
Sharp
Epson
Sanyo
Freescale
Sun Microsystems
Fijitsu
Sony
NEC
Symbian
Nokia
Texas Instruments
Intel
Toshiba
IBM
Wipro
Microsoft
… and many more
Source: ARM Website
Copyright (c) 2006 by Ajay Dudani 20
May not be reproduced or redistributed for commercial use.

21. ARM History
• Acorn Computer Group developed world’s
first RISC processor in 1985
• Roger Wilson and Steve Furber were the
principle developers
• ARM (Advanced RISC Machines) was a
spin out from Acorn in 1990 with goal of
defining a new microprocessor standard
Copyright (c) 2006 by Ajay Dudani 21
May not be reproduced or redistributed for commercial use.

22. ARM History (2)
• Acorn Computer Group
Source: Wikipedia
Copyright (c) 2006 by Ajay Dudani 22
May not be reproduced or redistributed for commercial use.

23. ARM History (3)
• ARM delivered ARM6 in 1991
– Introduced 32 bit addressing support
– New instruction for program status registers
– Variant used in Apple Newton PDA
• By 1996 ARM7 was being widely used
– Microsoft started port of WinCE to ARM
– Added multimedia extensions
• Exponential growth from then on…
Copyright (c) 2006 by Ajay Dudani 23
May not be reproduced or redistributed for commercial use.

24. ARM and StrongARM
• Intel gained certain IP from ARM as part of
lawsuit settlement and modified ARM
architecture branding it as StrongARM
• StrongARM name was changed to XScale
– Processor SA1000 , SA1100
• XScale is close to ARMv5 instruction set
• XScale division of Intel was sold to Marvel
Inc. in 2006
Copyright (c) 2006 by Ajay Dudani 24
May not be reproduced or redistributed for commercial use.

25. ARM Today
• ARM7xxx
– 3 stage pipeline
– Integer processor
– MMU support for WinCE, Linux and Symbian
– Used in entry level mobiles, mp3 players, pagers
• ARM9xxx
– 5 stage pipeline
– Separate data and instruction cache
– Higher end mobile and communication devices
– Telematic and infotainment systems
– ARM and Thumb instruction set
Copyright (c) 2006 by Ajay Dudani 25
May not be reproduced or redistributed for commercial use.

26. ARM Today (2)
• ARM11xxx
– 7 stage pipeline
– Trustzone security related extensions
– Reduced power consumption
– Speed improvements
– More DSP and SIMD extensions
– Used in PDA, smartphones, industrial
controllers, mobile gaming
Copyright (c) 2006 by Ajay Dudani 26
May not be reproduced or redistributed for commercial use.

27. ARM Processor Family
• ARM has devised a naming convention for
its processors
• Revisions: ARMv1, v2 … v6, v7
• Core implementation:
– ARM1, ARM2, ARM7, StrongARM,
ARM926EJ, ARM11, Cortex
• ARM11 is based on ARMv6
• Cortex is based on ARMv7
Copyright (c) 2006 by Ajay Dudani 27
May not be reproduced or redistributed for commercial use.

28. ARM Processor Family (2)
• Differences between cores
– Processor modes
– Pipeline
– Architecture
– Memory protection unit
– Memory management unit
– Cache
– Hardware accelerated Java
– … and others
Copyright (c) 2006 by Ajay Dudani 28
May not be reproduced or redistributed for commercial use.

29. ARM Processor Family (3)
• Examples:
– ARM7TDMI
• No MMU, No MPU, No cache, No Java, Thumb
mode
– ARM922T
• MMU, No MPU, 8K+8K data and instruction cache,
No Java, Thumb mode
– ARM1136J-S
• MMU, No MPU, configurable caches, with
accelerated Java and Thumb mode
Copyright (c) 2006 by Ajay Dudani 29
May not be reproduced or redistributed for commercial use.

30. ARM Processor Family (4)
• Naming convention
• ARM [x][y][z][T][D][M][I][E][J][F][S]
– x – Family
– y – memory management/protection
– z – cache
– T – Thumb mode
– D – JTAG debugging
– M – fast multiplier
– I – Embedded ICE macrocell
– E – Enhanced instruction (implies TDMI)
– J – Jazelle, hardware accelerated Java
– F – Floating point unit
– S – Synthesizable version
Copyright (c) 2006 by Ajay Dudani 30
May not be reproduced or redistributed for commercial use.

31. Outline
• ARM Technology
• ARM Tools & Products
• ARM Processor
• ARM Toolchain
• ARM Instruction set
• Thumb instruction set
• ARM exception and interrupts
• ARM Firmware
• Embedded operating system
• ARM Caches
• Memory management and protection
• ARM Future development
Copyright (c) 2006 by Ajay Dudani 31
May not be reproduced or redistributed for commercial use.

32. ARM Tools & Products
Disclaimer: All owners own their respective trademarks
Copyright (c) 2006 by Ajay Dudani 32
May not be reproduced or redistributed for commercial use.

33. ARM Chips
• ARM Ltd
– Provides ARM cores
– Intellectual property
• Analog Devices
– ADuC7019, ADuC7020, ADuC7021, ADuC7022, ADuC7024, ADuC7025,
ADuC7026, ADuC7027, ADuC7128, ADuC7129
• Atmel
– AT91C140, AT91F40416, AT91F40816, AT91FR40162
• Freescale
– MAC7101, MAC7104, MAC7105, MAC7106
• Samsung
– S3C44B0X, S3C4510B
• Sharp
– LH75400, LH75401, LH75410, LH75411
• Texas Instruments
– TMS470R1A128, TMS470R1A256, TMS470R1A288
• And others…
Copyright (c) 2006 by Ajay Dudani 33
May not be reproduced or redistributed for commercial use.

34. ARM Development Tools
Copyright (c) 2006 by Ajay Dudani 34
May not be reproduced or redistributed for commercial use.

35. ARM Single Board Computers
Copyright (c) 2006 by Ajay Dudani 35
May not be reproduced or redistributed for commercial use.

36. Recommended Text
• “ARM System Developer’s Guide”
– Sloss, et. al.
– ISBN 1-55860-874-5
• “ARM Architecture Reference Manual”
– David Seal
– ISBN 0-201-737191
– Softcopy available at www.arm.com
• “ARM system-on-chip architecture”
– Steve Fuber
– ISBN 0-201-67519-6
Copyright (c) 2006 by Ajay Dudani 36
May not be reproduced or redistributed for commercial use.

37. Outline
• ARM Technology Overview
• ARM Tools & Products
• ARM Processor
• ARM Toolchain
• ARM Instruction set
• Thumb instruction set
• ARM exception and interrupts
• ARM Firmware
• Embedded operating system
• ARM Caches
• Memory management and protection
• ARM Future development
Copyright (c) 2006 by Ajay Dudani 37
May not be reproduced or redistributed for commercial use.

38. ARM Design Philosophy
• ARM core uses RISC architecture
– Reduced instruction set
– Load store architecture
– Large number of general purpose registers
– Parallel executions with pipelines
• But some differences from RISC
– Enhanced instructions for
• Thumb mode
• DSP instructions
• Conditional execution instruction
• 32 bit barrel shifter
Copyright (c) 2006 by Ajay Dudani 38
May not be reproduced or redistributed for commercial use.

39. ARM Programming Model
• A=B+C
• To evaluate the above expression
– Load A to a general purpose register R1
– Load B to a general purpose register R2
– Load C to a general purpose register R3
– ADD R1, R2, R3
– Store R1 to A
Copyright (c) 2006 by Ajay Dudani 39
May not be reproduced or redistributed for commercial use.

40. Registers
• ARM has a load store architecture
• General purpose registers can hold data
or address
• Total of 37 registers each 32 bit wide
• There are 18 active registers
– 16 data registers
– 2 status registers
Copyright (c) 2006 by Ajay Dudani 40
May not be reproduced or redistributed for commercial use.

41. Registers (2)
• Registers R0 thru R12 are general R0
R1
purpose registers R2
R3
• R13 is used as stack pointer (sp) R4
R5
R6
• R14 is used as link register (lr) R7
R8
• R15 is used a program counter (pc) R9
R10
• CPSR – Current program status R11
R12
register R13 (sp)
R14 (lr)
R15 (pc)
• SPSR – Stored program status register CPSR
SPSR
Copyright (c) 2006 by Ajay Dudani 41
May not be reproduced or redistributed for commercial use.

42. Registers (3)
• Program status register
– CPSR is used to control and store CPU states
– CPSR is divided in four 8 bit fields
• Flags
• Status
• Extension
• Control
Copyright (c) 2006 by Ajay Dudani 42
May not be reproduced or redistributed for commercial use.

43. Registers (4)
• Program status register flags
– N:1 – Negative result
– Z:1 – Result is zero
– C:1 – Carry in addition operation
– C:0 – Borrow in subtraction operation
– V:1 – Overflow or underflow
Copyright (c) 2006 by Ajay Dudani 43
May not be reproduced or redistributed for commercial use.

44. Registers (5)
• Program status register controls
– I:1 – IRQ interrupts disabled
– F:1 – FIQ interrupts disabled
– T:0 – ARM Mode
– T:1 – Thumb Mode
Copyright (c) 2006 by Ajay Dudani 44
May not be reproduced or redistributed for commercial use.

45. Registers (6)
• Program status register control modes
– 0b10000 – User mode
– 0b10001 – FIQ mode
– 0b10010 – IRQ mode
– 0b10011 – Supervisor mode
– 0b10111 – Abort mode
– 0b11011 – Undefined mode
– 0b11111 – System mode
Copyright (c) 2006 by Ajay Dudani 45
May not be reproduced or redistributed for commercial use.

46. Processor Modes
• Processor modes are execution modes which determines
active registers and privileges
• List of modes
– Abort mode
– Fast interrupt mode
– Interrupt mode
– Supervisor mode
– System mode
– Undefined mode
– User mode
• All except User mode are privileged modes
– User mode is used for normal execution of programs and
applications
– Privileged modes allow full read/write to CPSR
Copyright (c) 2006 by Ajay Dudani 46
May not be reproduced or redistributed for commercial use.

47. Banked Registers
• Of total 37 registers only 18 are active in a given register mode
User/System Supervisor Abort FIQ IRQ Undefined
R0
R1
R2
R3
R4
R5
R6
R7
R8 R8_fiq
R9 R9_fiq
R10 R10_fiq
R11 R11_fiq
R12 R12_fiq
R13 (sp) R13_svc (sp) R13_abt (sp) R13_fiq (sp) R13_irq (sp) R13_und (sp)
R14 (lr) R14_svc (lr) R14_abt (lr) R14_fiq (lr) R14_irq (lr) R14_und (lr)
R15 (pc)
CPSR
SPSR SPSR_svc SPSR_abt SPSR_fiq SPSR_irq SPSR_und
Copyright (c) 2006 by Ajay Dudani 47
May not be reproduced or redistributed for commercial use.

48. Pipeline
• Pipelining is breaking down execution into
multiple steps, and executing each step in
parallel
• Basic 3 stage pipeline
– Fetch – Load from memory
– Decode – Identify instruction to execute
– Execute – Process instruction and write back
result
Copyright (c) 2006 by Ajay Dudani 48
May not be reproduced or redistributed for commercial use.

49. Pipeline (2)
•
Fetch Decode Execute
Cycle 1 ADD
Cycle 2 SUB ADD
Time
Cycle 3 CMP SUB ADD
Copyright (c) 2006 by Ajay Dudani 49
May not be reproduced or redistributed for commercial use.

50. Pipeline (3)
• ARM7 has a 3 stage pipeline
– Fetch, Decode, Execute
• ARM9 has a 5 stage pipeline
– Fetch, Decode, Execute, Memory, Write
• ARM10 has a 6 stage pipeline
– Fetch, Issue, Decode, Execute, Memory,
Write
Copyright (c) 2006 by Ajay Dudani 50
May not be reproduced or redistributed for commercial use.

51. Pipeline (4)
• In theory, each instruction is one
instruction cycle
• In practice, there is interdependency
between instructions
– Solution: instruction scheduling
Copyright (c) 2006 by Ajay Dudani 51
May not be reproduced or redistributed for commercial use.

52. Memory Protection
• Two modes for ARM memory protection
– Unprotected mode
• No hardware protection, software does protection of data
between tasks
– Protected mode
• Hardware protects areas of memory and raises exceptions
when policy is voilated
• ARM divides memory to regions and
programmer can set attributes on regions
• ARM provides mechanisms to define and set
attributes of regions programmatically
Copyright (c) 2006 by Ajay Dudani 52
May not be reproduced or redistributed for commercial use.

53. Memory Management
• ARM supports memory management and
virtual memory
• Programmatically access translation look-
aside buffers
• ARM memory management unit also
supports Fast Context Switching
Extensions that optimizes use of caches in
multitasking environments
• Details in later section
Copyright (c) 2006 by Ajay Dudani 53
May not be reproduced or redistributed for commercial use.

54. Outline
• ARM Technology Overview
• ARM Tools & Products
• ARM Processor
• ARM Toolchain
• ARM Instruction set
• Thumb instruction set
• ARM exception and interrupts
• ARM Firmware
• Embedded operating system
• ARM Caches
• Memory management and protection
• ARM Future development
Copyright (c) 2006 by Ajay Dudani 54
May not be reproduced or redistributed for commercial use.

55. Toolchain
• GNU Tools
– gcc – Front end to GNU compiler
– binutils – Binary tools
• ld – GNU Linker
• as – GNU assembler
• And others
– gdb – GNU Debugger
– uClib – Small footprint C Library
Copyright (c) 2006 by Ajay Dudani 55
May not be reproduced or redistributed for commercial use.

56. Toolchain (2)
• GCC
– Invoked language specific modules
– Invoked assembler and linker
– arm-elf-gcc command
• arm-elf-gcc test.c –o test
• arm-elf-gcc test.S –o test
Copyright (c) 2006 by Ajay Dudani 56
May not be reproduced or redistributed for commercial use.

57. Toolchain (3)
• GCC ARM specific options
– mapcs-frame: Generate ARM procedure call compliant stack
frame
– mbig-endian: Generate big endian code
– mno-alignment-traps: Generate code that assumes that
MMU does not trap on handling misaligned data
– mcpu=name : Specify CPU name; gcc can determine what
instructions it can use to generate output accordingly
– mthumb: Generate code for ARM Thumb mode
– msoft-float: Generate code assuming floating point hardware
is not present. Do floating point operation optimization in
software
– Refer to GCC manual page for more on compiler options
Copyright (c) 2006 by Ajay Dudani 57
May not be reproduced or redistributed for commercial use.

58. Inline assembly
• Developer can insert ARM assembly code
in C code – for example
printf (“Hello ARM GCC”);
__asm__ (“ldr r15, r0”);
printf (“Program may have crashed”);
Above code will corrupt program counter, so use
inline assembly carefully
Also, it may lead to non portable code
Copyright (c) 2006 by Ajay Dudani 58
May not be reproduced or redistributed for commercial use.

59. Inline assembly (2)
• Developer can force use of certain
registers using extended assembly
asm ( assembler template :
output operands /* optional */ :
input operands /* optional */ :
list of clobbered registers /* optional */ );
• Example:
int a = 10, b;
__asm__ (“mov %0, %1” :
“=r”(b) :
“=r”(a));
Copyright (c) 2006 by Ajay Dudani 59
May not be reproduced or redistributed for commercial use.

60. Inline assembly (3)
• Developer can request variable to be
assigned to specific register
register int regVar __asm__(“%r4”);
• Can be used with local and global
variables
• Need –ffixed-<reg> compiler option for
global variables
• Refer to GCC Inline Assembly reference for
more examples
Copyright (c) 2006 by Ajay Dudani 60
May not be reproduced or redistributed for commercial use.

61. GNU Toolchain
• Reference:
– www.gnuarm.org
– www.sourceware.org/binutils/
– www.gnu.org/software/gdb/
– www.sourceware.org/insight/
– www.uclibc.org
– GCC improvements for ARM
• www.inf.u-szeged.hu/gcc-arm/
Copyright (c) 2006 by Ajay Dudani 61
May not be reproduced or redistributed for commercial use.

62. ARM Toolchain
• ADS: ARM Developer Suite is older
version of compiler, assembler and linker
tools from ARM
• RCVT: Latest ARM compiler, assembler
and linker
Copyright (c) 2006 by Ajay Dudani 62
May not be reproduced or redistributed for commercial use.

63. ARM Toolchain
• ARM also provides support for RealView tools it
acquired as part of Keil acquisition
• JTAG Support: ARM provides debugging tools to
be used with JTAG supported hardware
• ETM Support: Embedded Trace Module is
hardware debug unit that extends on-target
debugging capabilities by providing extra
memory and registers for debugging purpose
• Refer to www.arm.com and www.keil.com/arm/
for details on ARM tools
Copyright (c) 2006 by Ajay Dudani 63
May not be reproduced or redistributed for commercial use.

64. Other Toolchains
• GNU X-Tools
– www.microcross.com
• IAR ARM Kit
– www.iar.com
• Intel Development Suite for XScale
– www.intel.com
Copyright (c) 2006 by Ajay Dudani 64
May not be reproduced or redistributed for commercial use.

65. Outline
• ARM Technology Overview
• ARM Tools & Products
• ARM Processor
• ARM Toolchain
• ARM Instruction set
• Thumb instruction set
• ARM exception and interrupts
• ARM Firmware
• Embedded operating system
• ARM Caches
• Memory management and protection
• ARM Future development
Copyright (c) 2006 by Ajay Dudani 65
May not be reproduced or redistributed for commercial use.

66. Outline
• ARM Technology Overview
• ARM Tools & Products
• ARM Processor
• ARM Toolchain
• ARM Instruction set
• Thumb instruction set
• ARM exception and interrupts
• ARM Firmware
• Embedded operating system
• ARM Caches
• Memory management and protection
• ARM Future development
Copyright (c) 2006 by Ajay Dudani 66
May not be reproduced or redistributed for commercial use.

67. Outline
• ARM Technology Overview
• ARM Tools & Products
• ARM Processor
• ARM Toolchain
• ARM Instruction set
• Thumb instruction set
• ARM exception and interrupts
• ARM Firmware
• Embedded operating system
• ARM Caches
• Memory management and protection
• ARM Future development
Copyright (c) 2006 by Ajay Dudani 67
May not be reproduced or redistributed for commercial use.

68. Exceptions
• Exception handling is a programming language or
hardware mechanism to catch runtime errors
• C++ and Java support exception handling in software
1. void func()
2. {
3. try
4. {
5. int a = 100/0;
6. }
7. catch(...)
8. {
9. cout << quot;Caught exceptionquot; << endl;
10. return;
11. }
12. cout << quot;No exception detected!quot; << endl;
13. return;
14. }
Copyright (c) 2006 by Ajay Dudani 68
May not be reproduced or redistributed for commercial use.

69. Exceptions (2)
• ARM support 7 exception modes
• Developers can write custom exception handlers
to deal with exception conditions
• For example:
– Consider a system that crashes if PC is corrupted.
This will cause an exception. In corresponding
exception handler, programmer can save state of all
registers to file system for debugging and reset
Copyright (c) 2006 by Ajay Dudani 69
May not be reproduced or redistributed for commercial use.

70. Exceptions (3)
• ARM Exceptions in order of priority
– Reset
– Data abort
– FIQ
– IRQ
– Prefetch abort
– Undefined instruction
– Software interrupt
Copyright (c) 2006 by Ajay Dudani 70
May not be reproduced or redistributed for commercial use.

71. Reset exception
• Highest priority exception
• The reset handler runs in supervisor mode
• Handler is generally located at
0x00000000
• In Reset handler, FIQ and IRQ are
disabled
• Other exceptions are not likely to occur
when in reset handler
Copyright (c) 2006 by Ajay Dudani 71
May not be reproduced or redistributed for commercial use.

72. Reset exception (2)
• Actions performed when reset is de-asserted
– R14_svc is set to unpredictable value
– SPSR_svc is set to unpredictable value
– CPSR[4:0] is 0b10011 – supervisor mode
– CPSR[5] is 0 – execute in ARM mode
– CPSR[6] is 1 – disable fast interrupts
– CPSR[7] is 1 – disable normal interrupts
– PC = 0x00000000
Copyright (c) 2006 by Ajay Dudani 72
May not be reproduced or redistributed for commercial use.

73. Data abort exception
• Data abort exception mean software is trying to read/write
an illegal memory location
• Data abort has higher priority than FIQ
• While handling this more, IRQ is disabled
• The abort handler should not cause further aborts
– Consider case of prefetch abort in abort handler
– This will cause abort handler to be reentered
• Abort handler is generally located at 0x00000010
Copyright (c) 2006 by Ajay Dudani 73
May not be reproduced or redistributed for commercial use.

74. Data abort exception (2)
• Actions performed on data abort
– R14_abt = address of abort instruction + 8
– SPSR_svc = CPSR
– CPSR[4:0] is 0b10111 – abort mode
– CPSR[5] is 0 – execute in ARM mode
– CPSR[6] is unchanged
– CPSR[7] is 1 – disable normal interrupts
– PC = 0x00000010
Copyright (c) 2006 by Ajay Dudani 74
May not be reproduced or redistributed for commercial use.

75. Fast interrupt
• FIQ exception mode exists if developer wants to
handle certain interrupts faster
• Additional banked registers in FIQ mode make
execution fast
• Higher priority in IRQ
• Disabled IRQ and FIQ
• Default ARM cores do not handle nested
interrupts
• FIQ handler is generally located at 0x0000001C
Copyright (c) 2006 by Ajay Dudani 75
May not be reproduced or redistributed for commercial use.

76. Fast interrupt (2)
• Actions performed on fast interrupt
– R14_fiq = address of next instruction to
execute + 4
– SPSR_fiq = CPSR
– CPSR[4:0] is 0b10111 – FIQ mode
– CPSR[5] is 0 – execute in ARM mode
– CPSR[6] is 1 – disable fast interrupts
– CPSR[7] is 1 – disable normal interrupts
– PC = 0x0000001C
Copyright (c) 2006 by Ajay Dudani 76
May not be reproduced or redistributed for commercial use.

77. Normal interrupt
• Normal interrupt is lower priority than fast
interrupts
• Disabled IRQ when handling normal
interrupts
• Default ARM cores do not handle nested
interrupts
• IRQ handler is generally located at
0x00000018
Copyright (c) 2006 by Ajay Dudani 77
May not be reproduced or redistributed for commercial use.

78. Normal interrupt (2)
• Actions performed on normal interrupt
– R14_irq = address of next instruction to execute + 4
– SPSR_irq = CPSR
– CPSR[4:0] is 0b10010 – IRQ mode
– CPSR[5] is 0 – execute in ARM mode
– CPSR[6] is unchanged
– CPSR[7] is 1 – disable normal interrupts
– PC = 0x00000018
Copyright (c) 2006 by Ajay Dudani 78
May not be reproduced or redistributed for commercial use.

79. Prefetch abort
• If processor reads instruction from undefined
memory, it causes a prefetch abort exception
• Prefetch abort occurs when instruction reaches
execution stage of pipeline
• Disabled normal interrupts when handling
prefetch abort
• Prefetch abort handler is generally located at
0x0000000C
Copyright (c) 2006 by Ajay Dudani 79
May not be reproduced or redistributed for commercial use.

80. Prefetch abort (2)
• Actions performed on prefetch abort
– R14_abt = address of next instruction to
execute + 4
– SPSR_irq = CPSR
– CPSR[4:0] is 0b10111 – abort mode
– CPSR[5] is 0 – execute in ARM mode
– CPSR[6] is unchanged
– CPSR[7] is 1 – disable normal interrupts
– PC = 0x0000000C
Copyright (c) 2006 by Ajay Dudani 80
May not be reproduced or redistributed for commercial use.

81. Undefined instruction
• When executing coprocessor instructions, ARM waits for
coprocessor to acknowledge that it can execute the
instruction
• If no coprocessor can handle given instruction, undefined
instruction exception is raised
• In simulators, this can be used to simulate coprocessor in
software
• Undefined instruction handler can parse instructions and
process them in software simulator
• Undefined instruction handler is generally located at
0x00000004
Copyright (c) 2006 by Ajay Dudani 81
May not be reproduced or redistributed for commercial use.

82. Undefined instruction (2)
• Actions performed on undefined instruction
– R14_und = address of next instruction to execute
– SPSR_und = CPSR
– CPSR[4:0] is 0b11011 – undefined mode
– CPSR[5] is 0 – execute in ARM mode
– CPSR[6] is unchanged
– CPSR[7] is 1 – disable normal interrupts
– PC = 0x00000004
Copyright (c) 2006 by Ajay Dudani 82
May not be reproduced or redistributed for commercial use.

83. Software interrupt
• Software interrupt exception is used to enter
supervisor mode to execute a privileged OS
function
• Typically applications run in user mode and
kernel in supervisor mode
• Execution of any system call will cause SWI
software interrupt to change mode to supervisor
mode
• Software interrupt handler is generally located at
0x00000008
Copyright (c) 2006 by Ajay Dudani 83
May not be reproduced or redistributed for commercial use.

84. Software interrupt (2)
• Actions performed on software interrupt
– R14_svc = address of next instruction to execute after
SWI
– SPSR_irq = CPSR
– CPSR[4:0] is 0b10011 – supervisor mode
– CPSR[5] is 0 – execute in ARM mode
– CPSR[6] is unchanged
– CPSR[7] is 1 – disable normal interrupts
– PC = 0x00000008
Copyright (c) 2006 by Ajay Dudani 84
May not be reproduced or redistributed for commercial use.

85. Exception table
• Memory layout
0x00000000 – reset exception handler
0x00000004 – undefined instruction handler
0x00000008 – software interrupt handler
0x0000000C – prefetch abort handler
0x00000010 – data abort handler
0x00000018 – normal interrupt handler
0x0000001C – fast interrupt handler
• High vectors
– Some implementation keep this table in 0xFFFF0000
to 0xFFFF001C range which is known as high vector
location
Copyright (c) 2006 by Ajay Dudani 85
May not be reproduced or redistributed for commercial use.

86. Exception handling
1. Exception is raised
2. Lookup to exception table to find exception handler
3. Exception handler is executed
4. Return from exception handler
Copyright (c) 2006 by Ajay Dudani 86
May not be reproduced or redistributed for commercial use.

87. Outline
• ARM Technology Overview
• ARM Tools & Products
• ARM Processor
• ARM Toolchain
• ARM Instruction set
• Thumb instruction set
• ARM exception and interrupts
• ARM Firmware
• Embedded operating system
• ARM Caches
• Memory management and protection
• ARM Future development
Copyright (c) 2006 by Ajay Dudani 87
May not be reproduced or redistributed for commercial use.

88. Outline
• ARM Technology Overview
• ARM Tools & Products
• ARM Processor
• ARM Toolchain
• ARM Instruction set
• Thumb instruction set
• ARM exception and interrupts
• ARM Firmware
• Embedded operating system
• ARM Caches
• Memory management and protection
• ARM Future development
Copyright (c) 2006 by Ajay Dudani 88
May not be reproduced or redistributed for commercial use.

89. Outline
• ARM Technology Overview
• ARM Tools & Products
• ARM Processor
• ARM Toolchain
• ARM Instruction set
• Thumb instruction set
• ARM exception and interrupts
• ARM Firmware
• Embedded operating system
• ARM Caches
• Memory management and protection
• ARM Future development
Copyright (c) 2006 by Ajay Dudani 89
May not be reproduced or redistributed for commercial use.

90. Outline
• ARM Technology Overview
• ARM Tools & Products
• ARM Processor
• ARM Toolchain
• ARM Instruction set
• Thumb instruction set
• ARM exception and interrupts
• ARM Firmware
• Embedded operating system
• ARM Caches
• Memory management and protection
• ARM Future development
Copyright (c) 2006 by Ajay Dudani 90
May not be reproduced or redistributed for commercial use.

91. Outline
• ARM Technology Overview
• ARM Tools & Products
• ARM Processor
• ARM Toolchain
• ARM Instruction set
• Thumb instruction set
• ARM exception and interrupts
• ARM Firmware
• Embedded operating system
• ARM Caches
• Memory management and protection
• ARM Future development
Copyright (c) 2006 by Ajay Dudani 91
May not be reproduced or redistributed for commercial use.

92. Outline
• ARM Technology Overview
• ARM Tools & Products
• ARM Processor
• ARM Toolchain
• ARM Instruction set
• Thumb instruction set
• ARM exception and interrupts
• ARM Firmware
• Embedded operating system
• ARM Caches
• Memory management and protection
• ARM Future development
Copyright (c) 2006 by Ajay Dudani 92
May not be reproduced or redistributed for commercial use.

93. Questions & Comments
Copyright (c) 2006 by Ajay Dudani 93
May not be reproduced or redistributed for commercial use.