Please implement the sequential circuit as Verilog code. State Diagram: State Table,
Assignment, and Minimal equation Please implement the sequential circuit as Verilog code.
Solution
`timescale 1ns/1ns
module SM101 (
clock,reset,w,
z);
input clock;
input reset;
input w;
tri0 reset;
tri0 w;
output z;
reg z;
reg [3:0] fstate;
reg [3:0] reg_fstate;
parameter A=0,B=1,C=2,D=3;
always @(posedge clock)
begin
if (clock) begin
fstate <= reg_fstate;
end
end
always @(fstate or reset or w)
begin
if (reset) begin
reg_fstate <= A;
z <= 1\'b0;
end
else begin
z <= 1\'b0;
case (fstate)
A: begin
if (~(w))
reg_fstate <= A;
else if (w)
reg_fstate <= B;
// Inserting \'else\' block to prevent latch inference
else
reg_fstate <= A;
z <= 1\'b0;
end
B: begin
if (~(w))
reg_fstate <= C;
else if (w)
reg_fstate <= B;
// Inserting \'else\' block to prevent latch inference
else
reg_fstate <= B;
z <= 1\'b0;
end
C: begin
if (~(w))
reg_fstate <= A;
else if (w)
reg_fstate <= D;
// Inserting \'else\' block to prevent latch inference
else
reg_fstate <= C;
z <= 1\'b0;
end
D: begin
if (~(w))
reg_fstate <= C;
else if (w)
reg_fstate <= B;
// Inserting \'else\' block to prevent latch inference
else
reg_fstate <= D;
z <= 1\'b1;
end
default: begin
z <= 1\'bx;
$display (\"Reach undefined state\");
end
endcase
end
end
endmodule // SM101.
Please implement the sequential circuit as Verilog code. State Diagr.pdf
1. Please implement the sequential circuit as Verilog code. State Diagram: State Table,
Assignment, and Minimal equation Please implement the sequential circuit as Verilog code.
Solution
`timescale 1ns/1ns
module SM101 (
clock,reset,w,
z);
input clock;
input reset;
input w;
tri0 reset;
tri0 w;
output z;
reg z;
reg [3:0] fstate;
reg [3:0] reg_fstate;
parameter A=0,B=1,C=2,D=3;
always @(posedge clock)
begin
if (clock) begin
fstate <= reg_fstate;
end
end
always @(fstate or reset or w)
begin
if (reset) begin
reg_fstate <= A;
z <= 1'b0;
end
else begin
z <= 1'b0;
case (fstate)
A: begin
2. if (~(w))
reg_fstate <= A;
else if (w)
reg_fstate <= B;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= A;
z <= 1'b0;
end
B: begin
if (~(w))
reg_fstate <= C;
else if (w)
reg_fstate <= B;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= B;
z <= 1'b0;
end
C: begin
if (~(w))
reg_fstate <= A;
else if (w)
reg_fstate <= D;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= C;
z <= 1'b0;
end
D: begin
if (~(w))
reg_fstate <= C;
else if (w)
reg_fstate <= B;
// Inserting 'else' block to prevent latch inference
else
3. reg_fstate <= D;
z <= 1'b1;
end
default: begin
z <= 1'bx;
$display ("Reach undefined state");
end
endcase
end
end
endmodule // SM101
![Please implement the sequential circuit as Verilog code. State Diagram: State Table,
Assignment, and Minimal equation Please implement the sequential circuit as Verilog code.
Solution
`timescale 1ns/1ns
module SM101 (
clock,reset,w,
z);
input clock;
input reset;
input w;
tri0 reset;
tri0 w;
output z;
reg z;
reg [3:0] fstate;
reg [3:0] reg_fstate;
parameter A=0,B=1,C=2,D=3;
always @(posedge clock)
begin
if (clock) begin
fstate <= reg_fstate;
end
end
always @(fstate or reset or w)
begin
if (reset) begin
reg_fstate <= A;
z <= 1'b0;
end
else begin
z <= 1'b0;
case (fstate)
A: begin](https://image.slidesharecdn.com/pleaseimplementthesequentialcircuitasverilogcode-230325175442-16ce4296/85/Please-implement-the-sequential-circuit-as-Verilog-code-State-Diagr-pdf-1-320.jpg)
