PRBS generation using four bit shift register ... Hardware design

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Lab Project (JOP792)
PRBS Generator Module
INSTRUCTORS
Prof. Vinod Chandra
Prof. V.K. Jain
Submitted by:
Ajay Singh (2014JOP2558)
Vishwaraj Esham (2014JOP2895)
Saheli Nargis (2014JOP2495)
Sirisha J. (2014JOP2496)

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Contents
1.Introduction[2]: ............................................................................................................................. 3
2.LFSR (Linear Feedback Shift Register)[1]:.......................................................................................... 4
2.1 FeedbackAction:...................................................................................................................... 5
2.2 Tapping Action: ....................................................................................................................... 5
3.Theoretical Overview of 4 bit feedback............................................................................................ 6
4.Hardware Implementation : ............................................................................................................ 8
5.Results:.......................................................................................................................................... 9
6.Further Extension: .........................................................................................................................11
7.Conclusion:....................................................................................................................................12
8.Reference:.....................................................................................................................................13
TABLE OF FIGURES:

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Figure 1:PRBS Generation Using 4 Bit Linear Feedback Shift Register (LFSR) using XOR gate[1]............... 5
Figure 2: Designed hardware............................................................................................................. 8
Figure 3:Circuit diagramfor PRBS generator module............................................................................ 9
Figure 4:Outputof PRBS generatorat CRO.(1),(2), (3),(4),(5) and (6) correspondtothe serial usedin
table2. .............................................................................................................................................10
Figure 5: Circuit diagram for generating desired sequence using parallel to serial conversion................11
Figure 6:Dutycycle correspondingtodifferentbitpatternusingdesiredsequencegenerator(using
parallel to serial convertor)...............................................................................................................12
1.Introduction[2]:
A source of ``random'' numbers is often needed to accomplish programming tasks. The reasons
for this are varied and sometimes surprising. In communication engineering PRBS has

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significant importance to optimise the designed system. Since the signal used for data
transfer/communication is of random nature ,we need to design a system which can work
efficiently with the random sequence. To optimise the system one need to check the system
with a random sequence.
Since computers act entirely predictable, it is not possible for a computer to generate truly
random numbers. Hence we generate processes which produce a stream of numbers which
look random even though they follow an entirely predictable pattern. These numbers are
pseudorandom in nature . There are many pseudorandom number generators, some of which
are extremely sophisticated. Encryption of data, for example, depends on pseudorandom
number generation for which finding any pattern in the number stream is extremely difficult. It
is important because almost everyone's financial security and privacy depends on the quality of
these pseudorandom number generator to generate corresponding pseudo random numbers.
Our pseudorandom number generator will not be of this quality. Here we are using just 8 bit
shifting process which leads to generate a pseudorandom sequence of 15 bits. It is a simple
shift register where the vacated bit is filled with the exclusive-or followed by NOT of two other
bits in the shift register.
2.LFSR (Linear Feedback Shift Register)[1]:
A PRBS bit stream can be generated by using a linear feedback shift register (LFSR). Figure 1
illustrates an example of a 4-bit LFSR and its shifting data pattern. When the shift register is
filled up with a seed pattern of all 1’s here, the table in the right hand side depicts how the
register contents change and put out a series of PRBS. Right after the final bit, it returns to the
top of the bit stream. There are 15 bits of pseudo random bit stream generated. An L-bit LFSR
generates (2L -1) bits of PRBS. With careful looking at the bit pattern in the shift register, you
can see there are all 4-bit combinations except all 0’s. If you feed the pattern of “0000”, the
shift register would be stuck and it generates only 0’s infinitely. So seed pattern must not be all
0’s. Hence, one of the 15 4-bit patterns can be accepted as a seed.

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Figure 1:PRBS Generation Using 4 Bit Linear Feedback Shift Register (LFSR) using XOR gate[1].
2.1 Feedback Action:
In an LFSR, the bits contained in selected positions in the shift register are combined in some
sort of function and the result is fed back into the register's input bit. By definition, the selected
bit values are collected before the register is clocked and the result of the feedback function is
inserted into the shift register during the shift, filling the position that is emptied as a result of
the shift. Feedback around an LFSR's shift register comes from a selection of points (taps) in the
register chain and by performing XNOR operation these taps provide tap(s) back into the
register. Register bits that do not need an input tap, operate as a standard shift register. It is
this feedback that causes the register to loop through repetitive sequences of pseudo-random
value. The choice of taps determines how many values there are in a given sequence before the
sequence repeats. The implemented LFSR uses a one-to-many structure, rather than a many-
to-one structure, since this structure always has the shortest clock-to-clock delay path. The
feedback is done so as to make the system more stable and free from errors. Specific taps are
taken from the tapping points and then by using the XNOR operation on them they are
feedback into the registers. 22 The bit positions selected for use in the feedback function are
called "taps". The list of the taps is known as the "tap sequence". By convention, the output bit
of an LFSR that is n bits long is the nth bit; the input bit of an LFSR is bit 1
2.2 Tapping Action:
An LFSR is one of a class of devices known as state machines. The contents of the register, the
bits tapped for the feedback function, and the output of the feedback function together

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describe the state of the LFSR. With each shift, the LFSR moves to a new state. (There is one
exception to this -when the contents of the register are all ones, the LFSR will never change
state.) For any given state, there can be only one succeeding state. The reverse is also true: any
given state can have only one preceding state. For the rest of this discussion, only the contents
of the register will be used to describe the state of the LFSR. A state space of an LFSR is the list
of all the states the LFSR can be in for a particular tap sequence and a particular starting value.
Any tap sequence will yield at least two state spaces for an LFSR. (One of these spaces will be
the one that contains only one state -- the all zero one.) Tap sequences that yield only two
state spaces are referred to as maximal length tap sequences. The state of an LFSR that is n bits
long can be any one of 2^n different values. The largest state space possible for such an LFSR
will be 2^n - 1 (all possible values minus the zero state). Because each state can have only once
succeeding state, an LFSR with a maximal length tap sequence will pass through every non-zero
state once and only once before repeating a state. One corollary to this behaviour is the output
bit stream. The period of an LFSR is defined as the length of the stream before it repeats. The
period, like the state space, is tied to the tap sequence and the starting value. As a matter of
fact, the period is equal to the size of the state space. The longest period possible corresponds
to the largest possible state space, which is produced by a maximal length tap sequence.
(Hence "maximal length")
The PRBS signal generated as above will have the following characteristics:-
1. The length of the sequence generated by it, m = (2N-1) , where N = number of bits (i. e., Flip-
flops) of the shift register,
2. After every m number of binary bits, the sequence will be repeating itself.
3.Theoretical Overviewof 4 bit feedback
The theoretical calculations of XNOR operation are given below in tables. Bit 1, Bit 2, Bit 3 and
Bit 4 corresponding to bits of shift register. Tap is used for giving feedback. The output is taken
from Bit 1. Initially we have considered 0000 so that XNOR can be proceed further.

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Bit 4 Bit 3 Bit 2 (Tap) Bit 1(Tap ) Bit 4 Bit 3(Tap ) Bit 2 Bit 1(Tap )
0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0
1 1 0 0 1 1 0 0
1 1 1 0 0 1 1 0
0 1 1 1 0 0 1 1
1 0 1 1 0 0 0 1
1 1 0 1 0 0 0 0
0 1 1 0 1 0 0 0
0 0 1 1 1 1 0 0
1 0 0 1 0 1 1 0
0 1 0 0 0 0 1 1
1 0 1 0 0 0 0 1
0 1 0 1 0 0 0 0
0 0 1 0 1 0 0 0
0 0 0 1 1 1 0 0
Bit 4(Tap ) Bit 3 Bit 2 Bit 1(Tap ) Bit 4 Bit 3(Tap ) Bit 2(Tap ) Bit 1
0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0
0 1 0 0 1 1 0 0
1 0 1 0 0 1 1 0
0 1 0 1 1 0 1 1
0 0 1 0 0 1 0 1
1 0 0 1 0 0 1 0
1 1 0 0 0 0 0 1
0 1 1 0 1 0 0 0
1 0 1 1 1 1 0 0
1 1 0 1 0 1 1 0
1 1 1 0 1 0 1 1
0 1 1 1 0 1 0 1
0 0 1 1 0 0 1 0
0 0 0 1 0 0 0 1

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Bit 4(Tap ) Bit 3 Bit 2(Tap ) Bit 1 Bit 4(Tap ) Bit 3(Tap ) Bit 2 Bit 1
0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0
0 1 0 0 0 1 0 0
1 0 1 0 0 0 1 0
1 1 0 1 1 0 0 1
0 1 1 0 0 1 0 0
0 0 1 1 0 0 1 0
0 0 0 1 1 0 0 1
1 0 0 0 0 1 0 0
0 1 0 0 0 0 1 0
1 0 1 0 1 0 0 1
1 1 0 1 0 1 0 0
0 1 1 0 0 0 1 0
0 0 1 1 1 0 0 1
0 0 0 1 0 1 0 0
Table 1. XNOR operation for different feedback from four bit shift register
4.Hardware Implementation :
The circuit diagram used for the generation of PRBS is shown below in fig 2.First the software
implementation was done in PSPICE then hardware was developed on breadboard. Finally the
circuit was designed on printed circuit board (PCB). Feedback was given from two of the shift
register at a time. Combination for different shift register feedback was chosen using a micro-
switch IC. Two pairs each of four switches were used for the purpose. At one time on only one
of the switch from each pair is made “on” rest of the six switches are kept “off”.
Figure 2: Designed hardware.

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Figure 3:Circuit diagram for PRBS generator module
5.Results:
The bit sequence output corresponding to the feedback is shown in table2. The output bit
pattern from the CRO is shown below in figure 3.
S.No. Feedback Output sequence
1 24 000010110000101
2 14 000010100110111
3 23 000011010001101
4 12 000011101100101
5 13 000011000011000
6 34 000010010010010
Table 2. Output Sequence corresponding to different feedback

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Figure 4:Output of PRBS generator at CRO. (1), (2), (3), (4), (5) and (6) correspond to the serial used in table2.

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6.Further Extension:
Known Sequence Generator: The prototype can also be extended to generate any of the
desired sequence of length of 8 bit, by extending the circuit . The circuit includes 8 single-way
micro switches and a parallel to serial convertor. Parallel to serial conversion can be done by
using IC 74165. The Circuit diagram is shown below. The Designed circuit/prototype can be
used for frequency division. The system can also be used to get a pulse with duty cycle of 1/8,
2/8, 3/8, 4/8, 5/8, 6/8 and 7/8.
Figure 5: Circuit diagram for generating desired sequence using parallel to serial conversion
frequency division can be done by choosing an appropriate bit pattern. Below in table
frequency division is shown corresponding to some of the bits patterns, where the state ot the
switch “open” is represented by 0 and “closed” state by 1 .
S.No. State of switches/Bit pattern Output Frequency
1 10101010 f/2
2 11110000 f/4
Table 3. Frequency division and corresponding bit pattern for parallel to serial conversion circuit ,

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Figure 6:Duty cycle corresponding to different bit pattern using desired sequence generator(using parallel to serial
convertor)
7.Conclusion:
The code for implementing the required PRBS is realized by writing PSPICE program. In the
program the logic implemented is very simple. A 8-bit PRBS is realized by shifting the input
through the D-flip flops and feed backing the outputs of some registers known as taps again
into the first register after passing them through a XNOR gate. The process of realizing LFSR is
carried out by first using Shift feedback resistor IC. The 4 bit shift register is used for the same.
The different output combinations of the shift resistor are then faded to the XNOR in order to
realise the output bit sequence. Tapings are taken from 1st, 2nd, 3rd and 4th Shift registers so
that the maximum length sequence of binary digits is produced. Initially when the reset is kept
at zero the outputs of each of the registers is uninitialized and hence the output is uninitialized
as well. However as soon as the reset is made high the output of all the registers start coming
out. A dead lock condition arises in the case when the initial input into the first register as
output of the XNOR gate are all 0’s.Under this condition the output of all the register of the
PRBS Generator remains as 1 at all instants of time. Therefore it is necessary that the initial
input to the PRBS Generator be equal to 0, the output of the XNOR gate. Maximum
randomness in the sequence was realised when the feedback was given from 1st
and 2nd
.shift

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registers.The code for implementing the above circuit was written and hence the simulation
results were generated and tested.
8.Reference:
[1] http://www.cs.miami.edu/~burt/learning/Csc609.022/random_numbers.html
[2] Tew, A. I. (2000). Digital Sequences, Correlation and Linear Systems, University of
York.Horowitz, P. & Hill, W. (1989). The Art of Electronics, Cambridge University Press, 2nd
edition.
[3] www.electronics.stackexchange.com.