The document summarizes a presentation given at an EMTP-RV user group meeting about developing HVDC models in EMTP-RV. It describes a detailed HVDC model that was developed including characteristics like converter transformers, converters, DC cables, filters, and control systems for the rectifier and inverter. Simulation results are shown. An average HVDC-VSC model is also described along with next developments.
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Edf R&D Dennetiere Hvdc Emtp
1. EMTP-RV user group meeting, Dubrovnik
HVDC models in
EMTP-RV
Sébastien Dennetière, EDF R&D, April 30th 2009
2. Presentation layout
Why do we develop HVDC models ?
Description of a detailed HVDC model in EMTP-RV
Simulation results
Description of an average HVDC-VSC model in EMTP-RV
Simulation results
Next developments
2 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
3. Why do we develop HVDC models ?
Growing interest in HVDC links in transmission system
Avoid overhead lines construction
Flexibility
HVDC links models are required :
Determination of the best HVDC solution in a specific case
Training of power system engineers
4 Models :
Detailed models for transient studies: generic & specific
Average models for system studies : generic & specific
3 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
4. Detailed HVDC model
Main characteristics :
Generic standard HVDC (Bipolar 12 pulses)
Rated power : 1200 MVA
DC voltage : +/- 500 kV
DC cable 1400 mm², 70 km
AC Filters : 11th, 15th, 23rd/25th ; DC Filters : 6th & 12th
Reactive power compensation : filters + capacitor bank
Smoothing reactor : 370 mH
AC Short Circuit Power : 6000 MVA
Control system :
Current controller on rectifier side
Gamma controller or current controller on rectifier side
Developed by : University of Ontario Institute of Technology ,
Ecole Polytechnique de Montreal and EDF R&D
4 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
5. Detailed HVDC model
L2
AC network : R1 + +
1.5 85mH
+
SCP = 6000 MVA 400kVRMSLL /_50
?v
AC filters:
Each filter and capacitor bank generate ¼ of reactive power
consumed by converters
Filters parameters are calculated from analytical expressions
included into scripts
ligne
PQ_capa_bank
PQ_HP
PQ_11
PQ_13
PQ
PQ
PQ
PQ
+
+
+
#C_24p#
#R_11#,#L_11#,#C_11#
#R_13#,#L_13#,#C_13#
Capacitor bank
+
#L_24p#
+
harmonic 11th harmonic 13th HP filter
#R_24p#
+
#C_bank#
5 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
7. Detailed HVDC model
DC Cables :
Paper insulated +/- 500 kV, 1400 mm²
CP model
DC filters : RLC branches ( 6th et 12th )
Smoothing reactance : 370 mH
RL4 cable_plus RL3
+ 500 kv +
1400 mm² Cu
0.139,370mH 0.139,370mH
DC filter DC filter DC filter DC filter
600 Hz 300 Hz 600 Hz 300 Hz
7 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
8. Detailed HVDC model
Rectifier / inverter control system
firing_rec_star
DEV7
Rectifier_inverter_control 1 1
a g1
b
VKSood g2 2 2
gamma_min_delta_bd dp 3 3
c g3
Regulation gamma_min_star_bd
gamma_min_delta_minus_bd
gamma_min_star_minus_bd
sp
dn
sn
out delay
width
g4
g5
blocking g6
4
5
6
4
5
6
id_rec idc
iref iref2 single firing of
iref1 io
6-pulse bridge
0.0002
scope Pulse generators
v_rec_c f(u)
scope
v_rec_b firing_rec_delta
scope DEV12
v_rec_a Fm8 a g1 1 1
1 VKSood 2 2
f(u) b g2
2
c g3 3 3
v_pri_rec_a 4 4
DEV6 Fm9 delay g4
1
f(u) width g5 5 5
5.3e-6 2
6 6
v_pri_a Fm11
blocking g6
v_pri_rec_b V_sync_a 1
Fm10
v_pri_b single firing of
V_sync_b 2 f(u) 1
v_pri_c f(u) 6-pulse bridge
5.3e-6 V_sync_c 3 2
v_pri_rec_c delta_freq
V.K.Sood Star/Delta
DQO_PLL_50Hz
3PH AC Line 5.3e-6 transformation
voltages at Rectifier
DEV9
v_pri_a
v_pri_b
v_pri_c
delta_freq
V_sync_a
V_sync_b
V_sync_c
1
2
3
Fm12
f(u) Pulse generation
Synchronization DQO_PLL_50Hz
V.K.Sood
DEV10
1Fm13
v_pri_a
V_sync_a 2 f(u)
v_pri_b
V_sync_b 3
v_pri_c
V_sync_c
delta_freq
V.K.Sood
DQO_PLL_50Hz
Synchronising System
C9
tap_changer_rec
205.45
c ratio_rec_Y
365
v2
v1
ratio_Y
ratio_D
ratio_rec_D Transformer tap changer
c
C10
8 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
9. Detailed HVDC model
Rectifier control system
from page 1
Initialization idc
sg10
step
Step Initialisation Div1
PI current Gain15
amplitude 1pu 1
width 4000ms 1000
f(s)
controller 180
time shift 200 ms Current
Scaling iref
iref
sg9 0.8111 deg_pu_delay
sum12
1.2 Gain17 0.81111
+ rc rv Int4 sum13
1 1
ramp
2
SUM + + 1 - + 10
!h
+ + 1
120
+ + !h deg_pu_delay_lim
Current order to be sent 0.2 lim8 0.0278 0.0278 lim7
Kp=1.65
Ramp Initialisation to inverter (page 3) Gain16 Ki=2.75 alpha_delay in seconds
amplitude 1pu via telecoms 0.7
divide by 120 elec. degs
width 150 ms Alpha rectifier limits:
time shift 50 ms alpha_min=5 degs =0.0278
alpha_max=145 degs=0.81111
sg3 err_idrec
scope
step step_change_Io
Iref
iref scope
Step change in Iorder
amplitude -0.1 pu
width 200 ms
time shift 501 ms
Step change in
Iorder
9 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
10. Detailed HVDC model
Inverter control system
Fm5
dp 1 0.2
sp 2 !h
MIN f(s) 1
dn 3 !h Users may select at the inverter either
sn 4 0.05 lim6
1. Inverter Gamma control, or
2. Inverter Current control. This is normally biased off
sg4
scope with the current margin setting
gamma_min
step
gamma_step
PI Gamma
Step Gamma test
amplitude 0.05 controller
width 300 ms
time shift 1400 ms
0.944
sum3
Step change in C12
c +
+
+
!h
- +
+ !h
Gain6
10
rc rv Int1
!h
+
sum5
+ 1
0.944
scope
Gain1
180 scope
sum4 + !h inv_gamma_controller alpha_inv_degs
Gamma order ref
Gamma
0.10 gamma_ref
scope
Gain5
0.711
Kp=0.75
0.711 lim4
beta_delay in seconds
1 V = 180 degs Ki=35.0
0.2 inv gamma divide by 120 electrical degs
0.1 = 18 degs MIN_SELECT Div2
1
MIN !h 1
2 120
inv current
Alpha inverter limits:
alpha-min-inv =110 degs = 0.611 pu
alpha-max-inv =170 degs = 0.944 pu
0.95
sum1
Div3 Gain4 0.925
rc rv Int3 sum2
idc 1
idc
1000
f(s)
!h
+ + 14
!h
+ + 1 scope
io - !h + !h inv_current_controller
0.711 lim1
current 0.611
scaling Kp=4.0
Gain3
Ki=12.0
1.8
sum8 sum6
0.95
+ + + + 1 scope
- - Io_inv
0.1 lim3
C9
Step Io test at rec sg6
c
0.1
PI current
amplitude 0.1 pu
width 270 ms step margin 0.1 pu simulates telecoms delay
for margin setting
controller
time shift 470 ms
10 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
11. Detailed HVDC model
EMTP-RV design
v(t) vd_rec_filtered
v_pri_rec_a scope V_pri_rec_a
v_pri_rec_b f(s) scope vd_rec_filtered V_pri_inv_a v(t)
scope v_pri_inv_a
v_pri_rec_c p3
v_pri_inv_b
v_pri_inv_c
vd_inv
400 kV AC system vd_rec scope scope id_rec
+VM
?v
ratio_rec_Y
vd_rec id_rec ratio_inv_Y 400 kV AC system
B6P_1
B6P_2
L2 YY1 RL4 v(t) i(t) cable_plus RL3
R1 +
PQ_AC_rec
1 2
6-pulse bridge p1 500 kv 6-pulse bridge
YY2
L1
+ PQ
+ + 1400 mm² Cu
+ - 2 1 PQ_AC_inv
1.5 85mH
3-phase
0.139,370mH 0.139,370mH
+ + R2
3-phase PQ
1.5
+
85mH
400kVRMSLL /_50 368/205.45 gamma_min_star_bd aux
+
?v aux gamma_min_star 410/205.45 400kVRMSLL /_0
firing_rec_star DC filter DC filter DC filter DC filter
PQ_pole1_rec gates - + gates firing_inv_star
PQ
600 Hz 300 Hz 600 Hz 300 Hz PQ_pole1_inv
PQ
ratio_rec_D
ratio_inv_D
PQ_filter_rec B6P_3
YgD_2 B6P_6
PQ PQ_filter_inv
6-pulse bridge YgD_3
1 2
+ + Pole - 6-pulse bridge 2 1
PQ
3-phase
3-phase
Rectifier AC Filters
368/205.45 gamma_min_delta_bd aux
aux gamma_min_delta 420/205.45 Inverter AC Filters
+
10M
AC filters firing_rec_delta gates -
harmonics + gates firing_inv_delta AC filters
R11
11, 13, 24+ harmonics
and 11, 13, 24+
Capacitor bank and
filters_rec ratio_rec_D
Capacitor bank
Rectifier filters_inv
B6P_4 ratio_inv_D
B6P_7
YgD_1
Filters sizing 6-pulse bridge YgD_4
1 2 6-pulse bridge
3-phase
+ - 2 1
3-phase
+
368/205.45 gamma_min_delta_minus_bd aux
aux gamma_min_delta_minus 10M 420/205.45
Filters sizing
firing_rec_delta PQ_pole2_inv
PQ_pole2_rec gates - - Pole + gates firing_inv_delta R19 PQ
PQ
ratio_rec_Y
ratio_inv_Y
B6P_5 B6P_8
YY9 YY4
6-pulse bridge
1 2
+ - 6-pulse bridge 2 1
3-phase 600 Hz 300 Hz 3-phase
600 Hz 300 Hz Inverter AC
aux DC filter DC filter aux
368/205.45 gamma_min_star_minus_bd DC filter DC filter gamma_min_star_minus 410/205.45 system
Rectifier AC system RL1 cable_minus RL2
firing_rec_star 500 kv firing_inv_star
gates - + 1400 mm² Cu
+ + gates
0.139,370mH 0.139,370mH
11 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
12. Detailed HVDC model
Simulation results
PLOT
PLOT
y
y
time (s) time (s)
Step change in Iorder Step change in Gamma order
Simulation options : Δt = 25µs, tmax = 2s, CPU time = 30s
12 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
13. Detailed HVDC model
Voltage sag
AC voltage rectifier side
PLOT
AC voltage inverter side
PLOT
y
y
time (s)
time (s)
DC Current
PLOT
DC Voltage
PLOT
y
y
time (s) time (s)
13 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
14. Detailed HVDC model, next developments
Available on demand
Implementation of the Voltage Dependent Current Limit Unit :
Static characteristic adapts Iref as a function of DC voltage
Dynamic characteristic adapts Iref as a function of DC voltage according to the
fast down time and slow up time
Modeling of protection systems (overvoltage, overcurrent, commutation
failures)
Implementation of start up algorithm
Integration of control systems designed by manufacturers (DLL
connection) to obtain specific HVDC models
14 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
15. Average HVDC VSC model
Main Characteristics :
Rated power : 1200 MVA
DC voltage : +/- 320 kV
DC cable 2500 mm² XLPE insulation, 70 km
Converters transformers
AC & DC filters
Capacitor bank : 20 µF
AC short circuit power : 6000 MVA
Control system :
Active power regulation
DC voltage regulation
Reactive power regulation
Developed by EDF R&D
15 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
16. Average HVDC VSC model
YY1 DC link YY2
AC_network2
LF + TD 1 2 2 1
+ + +
+ LF + TD
AC_network1 400/450 400/450
GND GND GND GND
HVDC_VSC_Link
F fault
3-phase fault during 200 ms
Q2_mes
scope
scope
P2_mes
Q1_mes
P1_mes
scope
scope
Load-flow
Load-flow
Initialization
Initialization
P2_mes Q2_mes
Q1_mes P1_mes
P Q
k_HVDC
Q P m_HVDC
+
+
V1 powerMeter2
powerMeter1 phase_2
phase_1
V_mag
V2_mag
V_mag V1_mag
XLPE_cable_1
+ CP
7.00000E+01
+
+
60uF 60uF
!v !v
+ +
+
+
Vdc1_mes Vdc2_mes
Idc1_mes
cI2 V V cI1 Idc2_mes
0.50/100
- - 0.50/100
+
+
60uF 60uF
!v 7.00000E+01 !v
+ CP
XLPE_cable_2
16 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
17. Average HVDC VSC model
PLOT
PLOT
y
y
time (s) time (s)
Active power step change DC voltage step change
Simulation options : Δt = 50µs, tmax = 3s, CPU time = 4.2s
17 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière
18. HVDC VSC model – Next developments
Reactive power controller has to be improved
Contribution to CIGRE WG B4.38 (Simulation of HVDC and FACTS)
Implementation of manufacturer controllers models using DLL
connection to obtain specific HVDC models
Available on demand
18 April 28th 2009, EMTP-RV UGM Dubrovnik, Sébastien Dennetière