6. Productivity Challenge for FPGA Designers Spend significant amount of time on system integration Core competency is innovation and product differentiation System integration Innovation Product differentiation
7. Improving Productivity- What It Means ? Do more with less—more complex products with same or less resources Reuse across projects—avoid obsolescence Reuse across locations Lower risk—avoid “throw-away” Reduce risk of design errors Reduce risk of market changes Reduce risk of schedule slips Allow customers to focus on their value-added core competencies
8. Tools to Improve Customer Productivity As FPGAs move to the heart of the system, design software plays a key role in defining customer productivity ALTERA Design Suite software tools leads the industry in several important areas Compilation time Timing analysis and Timing closure Power optimization and Power closure Team-based design methodology System-level design tools System Integration tools
10. Why Use System Integration Tools like Qsys? Simplifies complex system development Provides a standard platform supporting many IP cores Enables design re-use Raises the level of abstraction Allows developers to focus on “value add” instead of glue logic and system interconnect Scales easily to meet the needs of the end product Reduces time to market Reduces design development time Less error-prone Eases verification
24. Qsys Features High performance: New interconnect based on network-on-chip architecture Scalable systems: Hierarchical system design Industry-standard interfaces: Connect IP cores of different interfaces together (Avalon, AXI, AHB, etc.) Design re-use: IP management capabilities Faster board bring-up: Real-time system debug
31. Your SystemsIP 1 IP 2 IP 3 System 1 System 2 Design at a Higher Level of Abstraction by Integrating IPs and Systems
32. med low high off High Performance Interconnect SOPC Builder Qsys Manual Pipelining Manual Pipelining System Interconnect Fabric Higher Performance QsysInterconnect (Based on Network-on-chip Architecture)
35. Network-on-Chip (NoC) Architecture Packet transactions and transport Each command encapsulated in a packet to be sent to a slave Each response encapsulated in a packet to be sent back to a master Avalon-ST Avalon-MM Avalon-MM Master Network Interface Slave Network Interface Avalon ST Network (Command) Slave Interface Master Interface Master Network Interface Avalon ST Network (Response) Slave Network Interface Slave Interface Master Interface Transport Layer Transaction Layer Transaction Layer
44. TCP/IP Bridge IPC B D Read/Write Transactions Faster Board Bring-up with Real-TimeSystem Debug
45. Vision: Target Qsys Applications Qsys can be used in every FPGA design Control plane Reading and writing to control status registers Data plane Data switching (muxing, demuxing), aggregation, bridges
46. Summary Qsys increases design productivity through automated interconnect generation Faster design cycles Less design errors Easier verification Shorter time to market Qsys new features include: High performance interconnect with pipelinedNetwork-On-Chip architecture Scalable system design with hierarchy support Broad IP portfolio availability with industry-standard interfaces Design re-use with IP management capabilites Faster board bring-up with real-time debug capabilities
