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FPGA Based RGB LED Display
- 1. FPGA Based RGB LED Tiling System
- 2. Contents • System Overview • Digital Design • Software Design • Board Design
- 4. FPGA MODULE PC CONNECTIVITY STORAGE COMMUNICATION LOGIC & CONTROL FPGA
- 5. PC CONNECTIVITY • Serial Transfer :UART MODULE – RS 232 Protocol – Asynchronous Transfer – Full Duplex – Tested at baud rate of 9600bps to 115200bps
- 6. UART MODULE IMPLEMENTATION Marc STOP BIT START BIT MARC START BIT SIN=0 SIN=1 SIN=0 DATA 0 DATA 1 DATA 2 DATA 3 DATA 7 DATA 6 DATA 5 DATA 4 SIN=1 STOP BIT DATA
- 7. STORAGE • Block RAM – Dual Port – Default : 256 X 32bit RAM – Combined three to get 192 X 72bit RAM
- 8. STORAGE: ORGANISATION OF DATA LED 1.1 RED LSB(0) LED 1.1 BLUE LSB(0) LED 1.1 GREEN LSB(0) LED 1.2 RED LSB(0) LED 1.2 BLUE LSB(0) LED 1.2 GREEN LSB(0) LED 1.1 RED MSB(7) LED 1.1 BLUE MSB(7) LED 1.1 GREEN MSB(7) LED 1.2 RED MSB(7) LED 1.2 BLUE MSB(7) LED 1.2 GREEN MSB(7) LED 2.1 RED LSB(0) LED 2.1 BLUE LSB(0) LED 2.1 GREEN LSB(0) LED 2.2 RED LSB(0) LED 2.2 BLUE LSB(0) LED 2.2 GREEN LSB(0) LED 2.1 RED MSB(7) LED 2.1 BLUE MSB(7) LED 2.1 GREEN MSB(7) LED 2.2 RED MSB(7) LED 2.2 BLUE MSB(7) LED 2.2 GREEN MSB(7) LED 1.1 LED 1.2 LED 2.1 LED 2.2
- 9. COMMUNICATION • Inter-FPGA-Communication Module – Modified I2C Bus Interface • Two Wire Interface: Clock Signal and Data Signal • Duplex with Single Master • Connects 255 FPGAs – Required to relay images to FPGAs PC FPGA1 FPGA2 FPGA 4 FPGA 3 UART I2C
- 10. • Data transfer is initiated when data line is pulled low while Clock stays high. • The master puts new data on the falling edge • The slave receives data on the rising edge • Data Transfer is stopped by pulling the data line high while clock is constantly high Modified I2C : Timing
- 11. Start Signal • Clock=‘1’ • Data 0-1 Device Address • 1-255 Command Word • Bulk Transfer • Single Transfer • Address DATA • 576 Byte • 1 Byte Stop Signal • Clock=‘1’ • Data 1-0 Modified I2C : Message Protocol
- 12. LOGIC & CONTROL • PWM RAM Read Control • UART • I2C RAM Write Control
- 13. PWM Generation • Example – Generate 8 bit PWM • 0 means 0% duty cycle • 255 means 100% duty Cycle – Let us try and find PWM level of 128 • 128=010000000 • Hold the value of output= – bit 0 for 1 clock cycle – bit 1 for 2 clock cycle – bit 2 for 4 clock cycle – bit 3 for 8 clock cycle – bit 4 for 16 clock cycle – bit 5 for 32 clock cycle – bit 6 for 64 clock cycle – bit 7 for 128 clock cycle – Total clock cycles=255 • 128 would mean that we have 128 clock cycles for which the output is one and 127 cycles for which the output is 0 hence 50% duty cycle as required
- 14. PWM Generation + Read Control LED 1.1 RED LSB(0) LED 1.1 BLUE LSB(0) LED 1.1 GREEN LSB(0) LED 1.2 RED LSB(0) LED 1.2 BLUE LSB(0) LED 1.2 GREEN LSB(0) LED 1.1 RED MSB(7) LED 1.1 BLUE MSB(7) LED 1.1 GREEN MSB(7) LED 1.2 RED MSB(7) LED 1.2 BLUE MSB(7) LED 1.2 GREEN MSB(7) LED 2.1 RED LSB(0) LED 2.1 BLUE LSB(0) LED 2.1 GREEN LSB(0) LED 2.2 RED LSB(0) LED 2.2 BLUE LSB(0) LED 2.2 GREEN LSB(0) LED 2.1 RED MSB(7) LED 2.1 BLUE MSB(7) LED 2.1 GREEN MSB(7) LED 2.2 RED MSB(7) LED 2.2 BLUE MSB(7) LED 2.2 GREEN MSB(7) LED 1.1 LED 1.2 LED 2.1 LED 2.2
- 16. SOFTWARE DESIGN •Python •Pymedia •TERMINAL v1.9b •Serial Data Transfer •115200bps •Matlab Video Decoding Data Transfer GUI Utilities
- 17. Video Decoding • Any Image is a 3D array – Image(; ;1) represents RED – Image(; ;2) represents GREEN – Image(; ;3) represents BLUE • Any Video is a 4D array with time as the 4th dimension – Video(; ; ; N) where N represents the Nth frame
- 18. Our Mechanism 1 •Convert JPEG image to RGB Array 2 •Covert Array values to Binary Value 3 •Convert to RAM compatible format 4 •Generate a text file 5 •Transfer via Terminal at 115200bps
- 19. Our Mechanism 255 255 255 255 0 0 0 0 170 170 170 170 11111111 11111111 11111111 11111111 00000000 00000000 00000000 00000000 10101010 10101010 10101010 10101010 1 0 0 1 0 0 1 0 1 1 0 ASCII VALUE for 10010010
- 20. Python in Progress • Why Python? – Open Source and Free ware – Work: • Image Decoding • Data Transfer : PyUSB, PySerial • GUI Development: PyCard
- 21. LED Board • consists of matrix of RGB LEDs size – 24 X 24 RGB LEDs. FPGA Board • consists of power supply regulators, RS-232 Port, JTAG, 7-segment displays, buttons, and FPGA ( Spartan3AN-50K).
- 22. LED Board • Separation between RGB LEDs – 20mm. • Separate LEDs for each color because of cost factors • Board subdivided into 16 parts with 6 X 6 RGB LEDs • Board Specifications – Clearance – 10 mil – Width – 12mil – Drill size – 24 mil
- 23. • Multiplexing of LED Columns using High Power PMOS (FDC604P). • Power Supply - 5 V (Blue LEDs require 3.3 V) • NPN with every PMOS Since FPGA only Provides 3.3 V. LED Board
- 24. LED Board Layout
- 25. FPGA Board • Spartan3AN - XC3S50AN. – Package - Thin QFP with 144 pins (TQ144). • Power Supplies – VCCINT - 1.2V – VCCAUX – 3.3V • CLKIN – 20 MHz • Four Multiplexed - 7 Segment displays • RS- 232 Port along with MAX232 IC for signal interface with FPGA. • Four Buttons and three DIL switches as configuration selector.
- 28. Specifications of FPGA used • Device Name - XC3S50AN • System Gates -50K • Equivalent Logic Cells - 1,584 • CLBs - 176 • Slices - 704 • Distributed RAM Bits – 11k • Block RAM Bits - 54K • Maximum User I/O -108