L6561 Power Factor Corrector
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Introduction of the basic operations of the L6561 power factor corrector and its applications
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L6561 Power Factor Corrector
- 6. Error Amplifier & Overvoltage Detector Block
- 13. THD Corrector: Block Diagram The Total Harmonic Distortion (THD) of the line current is defined in percentage as:
- 14. Typical Application Circuit (80W, 110VAC)
- 15. Lighting Application with PFC
Notas del editor
- Welcome to the training module on STMicroelectronics’ L6561 Power Factor Corrector. This training module introduces the basic operations of the L6561 power factor corrector and its applications.
- L6561 is the improved version of the L6560 standard Power Factor Corrector. It has a superior performant multiplier making the device capable of working in wide input voltage range applications (from 85V to 265V) with an excellent THD. The start up current has been reduced to a few tens of mA and a disable function has been implemented on the ZCD pin, guaranteeing lower current consumption in stand by mode. Micro power start up current. Soft Output Over Voltage Protection. There is no need for an external low pass filter on the current sense and very low operating quiescent current minimizes power dissipation.
- The L6561 is an IC intended for controlling PFC pre-regulators. These are based on boost topology using the transition mode technique. The device is available in Mini DIP and SO8 packages. Although the IC is optimized for PFC pre-regulators in electronic lamp ballasts, AC-DC adapters and low power (150W) SMPS, its excellent performance and the extremely low external part count make it suitable in unconventional topologies/applications. The device features a true micro power start-up current (50 µA typical), a low quiescent current, a very precise internal reference (1% @ Tj=25 °C), an on-chip RC filter on the current sense pin and a multiplier with extended dynamics.
- The figure is the internal block diagram of the L6561, it is an IC intended to control PFC pre-regulators by using the Transition Mode technique. As shown in the figure, a linear voltage regulator supplied by Vcc generates an internal 7V rail used to supply the whole integrated circuit, except for the output stage which is supplied directly from Vcc. In addition, a bandgap circuit generates the precise internal reference (2.5V±1% @ 25°C) used by the control loop to ensure a good regulation. The undervoltage lockout (UVLO) comparator with hysteresis is used to enable the chip as long as the Vcc voltage is high enough to ensure a reliable operation. The Error Amplifier (E/A) inverting input, through an external divider connected to the output bus, compares the boosted output DC voltage, Vo, with the internal reference, so as to maintain the preregulator output DC voltage constant. A sophisticated two-level overvoltage protection is included and a disable function is available to shut down the device.
- The Error Amplifier (E/A) inverting input, through an external divider connected to the output bus, compares a proportion of the boosted output DC voltage, Vo, with the internal reference, so as to maintain the pre-regulator output DC voltage constant. The E/A output is used for frequency compensation, usually realised with a feedback capacitor connected to the inverting input. The E/A bandwidth will be extremely low because the output of the E/A must be constant over a line half-cycle to achieve a high PF. The L6561 is provided with a two-level overvoltage protection (OVP), realized by connecting to the E/A output. In case of overvoltage, the output of the E/A will tend to saturate low but the E/A response is very slow, so it will take a long time to go into saturation. On the other hand, an overvoltage must be corrected immediately. Hence a fast OVP detector, based on a different concept, is necessary. In steady state condition, the current through R1 is equal to the current in R2 because the compensation capacitor does not allow DC current to flow.
- The Zero Current Detection (ZCD) block switches on the external MOSFET as the voltage across the boost inductor reverses, just after the current through the boost inductor has gone to zero. A circuit is needed that turns on the external MOSFET at start-up since no signal is coming from the ZCD. This is realized with an internal starter, which forces the driver to deliver a pulse to the gate of MOSFET, producing also the signal for arming the ZCD circuit. The ZCD pin is used also to activate the Disable Block. If the voltage on the pin is taken below 150 mV the device will be shut down. As a result, its current consumption will be reduced. To re-enable the device operation, the pull-down on the pin must be released.
- The multiplier has two inputs: the first one takes a partition of the instantaneous rectified line voltage and the second one the output of the E/A. If this voltage is constant (over a given line half-cycle) the output of the multiplier will be shaped as a rectified sinusoid too. This is the reference signal for the current comparator, which sets the MOSFET peak current cycle by cycle.
- The current comparator senses the voltage across the current sense resistor (Rs) and, by comparing it with the programming signal delivered by the multiplier, determines the exact time when the external MOSFET is to be switched off. The PWM latch avoids spurious switching's of the MOSFET which might result from the noise generated. The output of the multiplier is internally clamped to 1.7V, (typ.) thus current limiting occurs if the voltage across Rs reaches this value.
- A totem pole buffer, with 400mA source and sink capability, allows driving an external MOSFET. An internal pull-down circuit holds the output low when the device is in UVLO conditions, to ensure that the external MOSFET cannot be turned on accidentally.
- The AC mains voltage is rectified by a diode bridge and the rectified voltage delivered to the boost converter using a switching technique which boosts the rectified input voltage to a regulated DC output voltage (Vo). The boost converter consists of a boost inductor (L), a controlled power switch (Q), a catch diode (D), an output capacitor (Co) and, a control circuitry. The goal is to shape the input current in a sinusoidal fashion, in-phase with the input sinusoidal voltage. To do this the L6561 uses the so-called Transition Mode technique.
- The ability to operate under large variations of both input voltage and load current, as well as the use of PFC systems as pre-regulators for switching converters, requires a more accurate design of the control loop. The goal will not only be to ensure a narrow bandwidth in order to achieve a high Power Factor, it is also to have enough phase margin to make sure the system is stable over a large range of operating conditions. Here shows Block diagram of control loop of L6561 device. The loop gain of PFC preregulators must have a very low crossover frequency to maintain V COMP (Error Amplifier output) fairly constant over a given line cycle and ensure a high PF. The error amplifier has been compensated to get a type 2 amplifier that provides a pole at the origin and a zero-pole pair.
- Here shows the THD corrector circuit block diagram and the waveforms in the significant points; the multiplier has two inputs: the first one is a fraction of the rectified input voltage and the second one is the output of error amplifier. The multiplier output is the product of these two quantities and (ideally) is a rectified sinusoid whose peak amplitude decreases by increasing the input voltage. Essentially the THD improvement circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid.
- This slide is an Application circuit diagram of L6561 device for 80W, 110VAC. The design of an 80W power-factor-corrected AC-DC adapter suitable for hi-end portable computer.
- In this configuration, the L6561 is used as power factor corrected preregualtor for electronic ballast applications. In the circuit as shown, the AC mains voltage is rectified by a diode bridge and delivered to the boost converter. The converter section boosts the rectified voltage to a DC controlled value. The section consists of a boost inductor (T1), a controlled power switch (Q1), a boost diode (D1), an output capacitor (C5) and control circuitry. The output voltage value of the PFC is adjustable by the R7-R8 resistor pair .
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