Conference on Adaptive Hardware and Systems (AHS'14) - The FlexTiles Embedded FPGA

www.flextiles.eu
FlexTiles
Dynamically Reconfigurable Embedded
FPGA System
2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS’14)
FlexTiles Workshop - July 18th 2014
Antoine COURTAY, Olivier SENTIEYS★, Christophe HURIAUX
 University of Rennes 1
★ Inria

2 /
TheinformationcontainedinthisdocumentandanyattachmentsarethepropertyofFlexTilesconsortium.Youareherebynotifiedthatanyreview,dissemination,distribution,
copyingorotherwiseuseofthisdocumentmustbedoneinaccordancewiththeCAoftheproject(TRT/DJ/624412785.2011).Templateversion1.0
University of Rennes 1 – AHS’14 FlexTiles Workshop 29
Outline
eFPGA Reconfigurable Fabric
 General architecture overview
 Expected features
 Task migration in FPGA vs. task migration in eFPGA
 Efficient hardware task swapping
 eFPGA architecture
Virtual Bit-Stream
What about heterogeneous blocks ?
Development flow
Results & conclusion

3 /
General Architecture Overview

4 /
Expected Features
Main expected features
 Low reconfiguration time (and power) overhead
 Low complexity reconfiguration control
 Resource sharing/distribution easiness, simplified task migration
 No predefined configuration domains
 Smaller bit-stream size in configuration memory
 Virtual Bit-Stream (VBS)
In contrast to state-of-the-art FPGA
 No predefined reconfigurable regions
 Bit-stream independent from task location

5 /
Task Allocation & Migration in FPGA
 Predefined
reconfigurable regions
 Bit-stream depends on
task location
I/O I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/OI/OI/OI/OI/OI/OI/OI/O
I/O
I/O
HW Accelerator #1
BS #1
HW Accelerator #1
BS #2

6 /
Task Migration in eFPGA
3D NI3D NI
3DNI3DNI
RAM RAM RAM RAM
RAM RAM RAM RAM
3DNI3DNI
3D NI
3DNI
3DNI
3D NI
3DNI
3DNI
3D NI
3DNI
3DNI
HW Accelerator #2
BS #2
HW Accelerator #1
BS #1

7 /
Efficient Hardware Task Swapping
Hiding reconfiguration time with computing
 Single-context memory
 Double-context memory
 eFPGA will use double-context memory
 Gain in dynamic reconfiguration efficiency
 At the cost of ~50% overhead
Task 1 Task 2
time
Cfg. 2Cfg. 1
Task 1 Task 2
time
Cfg. 2Cfg. 1
CB
FF
ConfClk Latch
ConfEn
CB
CB: one configuration bit

8 /
eFPGA Architecture
Logic Block
Switch Block
LUTCLBIN
ScanIn
FF
mux
C
B
ScanOut
CLBOUT
clk,rstbC
B
C
B
C
B
C
B
NORTH(i)
SOUTH(i)
EAST(i)WEST(i)
ScanIn
ScanOut

9 /
eFPGA Architecture
Interconnection Block
CLBIN[1
]
CLBIN[2]
CLBIN[3] CLBOUT
CLBIN[0]
NORTH
0 1 2 3
0 1 2 3
SOUTH
0123
WEST
EAST
0123

10 /
eFPGA Architecture
eFPGA macro
CHANY
(i,j+1)
SB
(i-1,j)
CHANX
(i+1,j)
CLB
(i+1,j)
SB
(i,j-1)
SB(i,j)
CLB
(i,j+1)
CLB
(i,j)
CLBIN[1]
CLBIN[2]
CLBIN[0]
CLBIN[3] CLBOUT
CHANX(i,j)
CHANY(i,j)
CLBIN[3] CLBOUT
CLBIN[0]

11 /
Outline
Virtual Bit-Stream
 Virtual Bit-Stream overview
 Interconnection architecture
 Routing details abstraction
 Results
Development flow

12 /
eFPGA Architecture using VBS
Reconfiguration controller finalizes VBS
Reconfiguration
controller
External
memory
VBS
1
VBS
2
VBS
3
VBS
N
Buffer
memory
data
control
1
2

13 /
Interconnection Architecture
Hiding routing details
 Full BS is 129 bits
 Could be reduced by giving
less details
CLBIN[1
]
CLBIN[2]
CLBIN[3] CLBOUT
CLBIN[0]
4 5 6 7
12 13 14 15
0123
891011
16
17
18
19 20

14 /
Virtual Bit Stream
Hiding routing details
 List of I/O and connections
 20  8
 1  9
 5  18
4 5 6 7
12 13 14 15
0123
89101116
17
18
19 20

15 /
Results
VBS is independent of task location
VBS has a smaller size than BS
 Compression ratio between 25% and 50%
 More efficient on large bit-streams
 Still improving…
 Work on reducing coding of connections

16 /
Outline
Virtual Bit-Stream
 Task placement in a homogeneous context
 Heterogeneous case
Development flow

17 /
Task placement in a homogeneous context
Homogeneous case
 This is the easiest case:
 No constraint on task placement
 Regular routing architecture
 Low impact on the reconfigurable architecture
Task
Configured LE
Logic Element (LE)

18 /
eFPGA : Complex blocks handling
Heterogeneous case
 Main goal:
 Place tasks on the logic fabric with as much flexibility as possible
 Introduce RAM blocks, DSP, 3DNI+AI
 Why not sticking to the classic task placer (i.e. homogeneous) ?
 It doesn’t work ! Flexibility is greatly reduced.

19 /
Proposal
 Heterogeneous blocks routing is abstracted from logic routing
 Long lines allow a trade-off between placement flexibility and
routing complexity
 A two-level routing is performed at runtime:
 Logic routing, as in the homogeneous case
 Heterogeneous block routing through long lines

20 /
Advantages
 We can handle complex blocks 
 The logic can be slided around a complex block because of the
connections to long lines

21 /
Constraints
 Delay can only be estimated offline (but the online placer could be
constrained)
 Flexibility limited to one axis. On the other axis tasks have to be
moved on heterogeneous block thresholds
 Connections to complex blocks (long lines) should be constrained
on specific lines

22 /
Outline
Virtual Bit-Stream
Development flow

23 /
Development Flow
Custom development flow from C to Virtual Bit-Stream
High-level Synthesis
High-level task
description
RTL task description
HDL Synthesis
HDL task description
Flat logic netlist
Technology mapping
Mapped logic netlist
Placer Router
Placement
data
Routing
data
Arch.
netlist
Bitstream generation
Virtual bit-stream
Arch.
description
 Integrated within the
FlexTiles
development flow
 Generates VBS from
a C description or a
HDL description

24 /
Development Flow
 Relies on Catapult C
from Calypto Design
Systems
 High-level synthesis
from C to VHDL

25 /
Development Flow
 Use the Verilog To
Routing (VTR)
academic tool flow
to generate netlist
and routing data
from Verilog
RTL task description
HDL Synthesis
HDL task description
Flat logic netlist
Technology mapping
Mapped logic netlist
Placer Router
Placement
data
Routing
data
Arch.
netlist
Arch.
description

26 /
Development Flow
 A custom back-end
generate the VBS
from the data
generated by VTR
 The VBS can be
loaded on the
FlexTiles platform

27 /
Outline
Virtual Bit-Stream
Development flow

28 /
Results
Overall results and achievements
 3-D stacked embedded FPGA coupled to a processor layer
 Flexible resource allocation/sharing
 Seamless task migration
 VBS also reduce the bitstream size

29 /
Results
Thank you for your
attention.

Conference on Adaptive Hardware and Systems (AHS'14) - The FlexTiles Embedded FPGA

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