Más contenido relacionado La actualidad más candente (20) Similar a Integrating a custom AXI IP Core in Vivado for Xilinx Zynq FPGA based embedded systems (20) Más de Vincent Claes (20) Integrating a custom AXI IP Core in Vivado for Xilinx Zynq FPGA based embedded systems1. Integrating a custom AXI IP Core
in Vivado for Xilinx Zynq FPGA
based embedded systems
Vincent Claes
6. XDC (Xilinx Design Constraint File)
##Switches
set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=SW1
set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3
##Pmod Header JE
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1
set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4
set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8
set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9
set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10
Vincent Claes
35. Add port to dobbelsteen_v1_s00_AXI
component
Vincent Claes
36. Port map in dobbelsteen top VHDL file
Vincent Claes
39. File Groups (Extra – not in this project)
If you use IP from the Xilinx IP
Catalog don’t forget to Add
Sub-Core References in your
File Groups!!!
For instance when using the
clock wizard inside your
Custom VHDL IP block!
Vincent Claes
Notas del editor Integration of custom IP core (VHDL)
Xilinx Zynq based
Digilent Zybo board Hardware connection of Dice PCB board
JE Pmod connector is used ------------------------------------------------------------------------------------ Company: -- Engineer: Vincent Claes -- -- Create Date: 07.10.2016 16:16:53-- Design Name: -- Module Name: Dobbelsteen - Behavioral-- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision:-- Revision 0.01 - File Created-- Additional Comments:-- ----------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity Dobbelsteen is Port ( sw : in STD_LOGIC_VECTOR (3 downto 0); je : out STD_LOGIC_VECTOR (7 downto 0));end Dobbelsteen;architecture Behavioral of Dobbelsteen isbegin-- je[0] = LED 1 - JE1-- je[1] = LED 2 - JE2-- je[2] = LED 3 - JE3-- je[3] = no conn-- je[4] = LED 4 - JE7-- je[5] = LED 5 - JE8-- je[6] = LED 6 - JE9-- je[7] = LED 7 -JE10--##Pmod Header JE--set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1--set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2--set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3--set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4--set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7--set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8--set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9--set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10-- 1 => LED 4-- 2 => LED 1 LED 7-- 3 => LED 1 LED 7 LED 4-- 4 => LED 1 LED 3 LED 5 LED 7-- 5 => LED 1 LED 3 LED 4 LED 5 LED 7-- 6 => LED 1 LED 2 LED 3 LED 5 LED 6 LED 7process(sw)begin case (sw) is when "0001" => --1 je <="00010000"; when "0010" => --2 je <="10000001"; when "0011" => --3 je <="10010001"; when "0100" => --4 je <="10100101"; when "0101" => --5 je <="10110101"; when "0110" => --6 je <="11100111"; when others => je <=(others=>'0'); end case; end process; end Behavioral; Create new project Next button Project Name
Project Location
Create project subdirectory
Next button
RTL Project
You can select “Do not specify sources at this time”, otherwise more windows appear
Next button Target language = VHDL
Simulator language = VHDL
Next button Next button Next button Select boards
Zybo board (xc7z010clg400-1)
Next button Finish button Select IP – General Tab and look at my settings, be sure those are the same. In the Packager Tabs unselect the option “Delete project after packaging”
I always enable the “Create archive of IP” option to have a backup plan Following section explains the creation of a custom VHDL dice ip core Select Tools
Create and Package IP …, this starts a wizard to create a new AXI IP Next button Select “Create a new AXI4 peripheral”
Select the Next button Specify the name, version and description for the new peripheral
Don’t forget to check the IP Location
Click Next Click Next button Select “Edit IP”
Finish button Select Add Sources from Project Manager in the Flow Navigator window Select Add or Create design sources
Click next Select Add Files Browse to your VHDL Dice Controller file and select thisone, press OK button
Select Finish button Dobbelsteen is dice in Dutch language component Dobbelsteen is
Port ( sw : in std_logic_vector(3 downto 0);
je : out std_logic_vector(7 downto 0));
end component dobbel: Dobbelsteen
port map( sw=> slv_reg0(31 downto 28),
je => je);
Je : out std_logic_vector(7 downto 0); Je : out std_logic_vector( 7 downto 0); Select Package IP from Project Manager (Flow Navigator Window) Select File Groups
Select “Merge changes from File Groups Wizard”
Add Sub-Core Reference
“Clocking wizard” for instance Select “Merge changes from Customization Parameters Wizard” Select “Re-Package IP” Select “Yes” Check the Repository Manager of the IP in the Project Manager Select “Create Block Design” from “IP Integrator” in the Project Manager Tab of the “Flow Navigator”. Specify a Design name (for instance default design_1)
I never change those settings.
Select ok Select the Add IP option to add a PS ZYNQ core to the block design Select ZYNQ7 Processing System Select Run Block Automation Block diagram is auto updated by use of Block Automation feature of Xilinx Vivado IDE Select Add IP Add dobbelsteeen_v1.0 axi ip core Click on Run Connection Automation to Auto create AXI bus Master Slave structure between PS7 and Dobbelsteeen ip. Click OK button Right mouseclick on je output of dobbelsteeen_0 Select make external to make the je[7:0] pins connection the the board (outside world on je connector of Zybo board) Select “Create HDL Wrapper” Let Vivado manage wrapper and auto-update
Select ok button Select add sources from Project manager in the Flow Navigator window Select Add files from the Add or Create constraint window
Be sure to select the XDC file with the je connector and sw uncommented It’s time to grab a cup of coffee and start to generate the bitstream Select Yes Select Cancel Select Export Hardware from File Set Include the bitstream option
Select the ok buttn Select “Launch SDK” from file Select ok Hdf file => look for dobbelsteeen in the address map Start a new application project Select Next Select Hello World Template and Click Finish button