This document discusses the development of a modular electronics system using FPGAs to enable the rapid design of humanoid robotic subsystems. It proposes a distributed network of FPGA modules with each limb containing an FPGA board to control sensors and actuators. A central controller based on an FPGA and ARM processor acts as a hub to interconnect the modules. Experimental results show the system can achieve high-performance motor control, multi-DOF stereo vision control, and low-latency communication between modules. The conclusion is that the modular FPGA approach can meet requirements for building humanoids by enabling flexible control of limbs and high-speed communication between distributed components.

1. Versati l e Modul ar El ectroni cs For Rapi d Desi gn And
Devel opment of
HUMANOID ROBOTIC SUBSYSTEMS
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By
Gokul G Nair
gokul.vtra@gmail.com

2. 1. INTRODUCTION
2. CURRENT SCENARIO IN HUMANOID DEVELOPMENT
3. REQUIREMENTS FOR COMPACT HUMANOID ELECTRICAL SYSTEM
4. DEVELOPMENT PATH TO MEET THE REQUIREMENTS
5. WHAT IS FPGA……….?
6. WHY FPGA……?
7. SYSTEM OVERVIEW
1) FPGA MODULE
2) CONTROL BOARDS
3) CENTRAL CONTROLLER
4) COMMUNICATION
8. DISCUSSIONS AND EXPERIMENTAL RESULTS
9. CONCLUSION
10. REFERENCES
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3.  Humanoid robot- Robot with its body shape built to resemble that of a human
 Generally humanoids have a torso, a head ,
2 arms & 2 legs
 Though some may model only part of a body
E.g.: From the waist up
 Development is a complex procedure
• Numerous subsystems needs to be
combined for actuation
• Subsystems - electric motors, hydraulic
valves , sophisticated sensors etc.
 AIM
Simplification of development and up gradation of these
humanoids by the use of Modular Electronic
Components (FPGA)
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4. I N H U M A N O I D D E V E L O P M E N T
 Low level controllers distributed across the humanoid system-
 Results in reduction of cables & increased compactness
How to handle with minimal latency, the vast quantity of information that needs
to be communicated to the central processing unit, while also ensuring a fully
operational system at the same time?
H i g h P r i o r i t y C o m p a c t n e s s
 Humanoid system developers placed high priority on
compactness
 Results in reduction of overall system’s size and weight
 Main challenge is to “reduce the amount of electrical cables
running from the actuators and sensors to a centralised
controller”
D i s t r i b u t e d A p p ro a c h
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5. REQ U I R E M E N T S
COMPACT HUMANOID ELECTRICAL SYSTEM
 Distributed controllers capable of
interfacing with all sensors and
actuators on a single limb
 Compact electrical design for
minimizing size and weight
 Capability of high frequency, hard real
time control loops
 High speed, low latency
intercommunication between limbs
 Clear development pat
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6. DEVELOPMENT PATH
T O M E E T T H E R E Q U I R E M E N T S
 selection of the embedded processor and its complimentary specialist components
 Essentially allow us to “plan ahead” for future changes
 Accommodate the increasing processing load of humanoids.
 DSP
 FPGA
 PIC
 ARM
 Architectures under consideration
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7. WHAT IS FPGA……….?
 A field-programmable gate array (FPGA) is an integrated circuit designed
to be configured by a customer or a designer after manufacturing hence
“field-programmable”
 Contain programmable logic components called "logic blocks", and
interconnects.
 FPGA chips handle dense logic and memory elements offering very high
logic capacity
 Can be configurable without change their hardware
 Vendors: Xilinx, Altera, Actel
 FPGA products:- Xilinx Virtex-7 FPGA, Spartan-6 LXT FPGA & Stratix V from Altera
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8. WHY FPGA……?
 Performance
 Time to Market
 Cost
 Reliability
 Long-Term Maintenance
Size comparison of the Spartan 6 USB-FPGA Module .
Heat sinks are delivered with the LX45
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9. SYSTEM OVERVIEW
 Heart of system is a distributed network of FPGA modules.
 Every limp has a FPGA module and which are networked
together in a star formation..
 Star network has a “Central controller” in the center Which is
a combination of FPGA and duo core ARM processors.
 ARM processors are running FreeRTOS which is a real-time OS
on one core, that takes care of the low level control and
Ubuntu on the second core.
 An Ethernet connection from the central controller to the
High-Level PCs where all the cognitive processing is computed.
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10. FPGA MODULE
 FPGA module is based around an Xilinx Sparten 6 FPGA
 currently consists of:
• Xilinx Spartan-6 LX45 FPGA.
• 6 axis IMU, MPU-6050.
• 8 Channel ADC, ADS8332.
• 2 x Full-duplex 200 Mb/s interconnection.
• 128Mb SPI Flash.
• 70 I/O, User configurable.
• 17 programmable LEDs
• Size: 35mm x 35mm.
• Weight: 8g
Version 2.0 of the FPGA Module
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11. 2) CONTROL BOARDS
 Each limb has its own electrical
requirements due to different actuators and
sensors.
 Thus each limb has a custom control board.
1) Low Amp BLDC controller.
 control a 3 DoF neck, which had a brushless
motor which communicated via hall effect
sensors and a digital encoder in each joint
2) Brushed Motor Driver.
 very simple 2 layer board developed for
controlling a pair of eyes with 2 DoF each.
3) High Current BLDC Controller.
 developed for the thigh, which has high power
requirements
 interface with the frameless motors that have
their own magnetic encoders.
 interface with the foil strange gauges used to
measure the torque at the joint
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3) CENTRAL CONTROLLER
 Central hard real-time controller based on a
Xilinx Zynq-XC7Z020
 An FPGA and dual core ARM “A9 MP Core”
processor running at 667MHz on a single
chip.
 Includes 512MB of DDR3 RAM, Gigabit
Ethernet, USB and an SD card reader.
Central hard real-time controller based on a Xilinx Zynq-XC7Z020
 The central controller has 6 high speed communication ports as well as interfaces for a
range of sensors
 The FPGA fabric is used primarily for the communication to the other FPGA modules e.g.
acting like an intelligent hub.
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13. CENTRAL CONTROLLER CONTINUES
The ARM processors is configured in an asymmetric multi-processing (AMP) configuration, with
two separate OS running on each core
Overview of central controller hardwareFIRST CORE
 For hard real time control loop
 This loop used for scheduling the network communication as well as the low level control (Requires
a fast update) and hard real time. {E.g. the walking and balancing controller. }
 Runs RealRTOS, an open source real time operating system.
SECOND CORE
 Runs UBUNTU and Robot Operating System (ROS)
 Used for the soft real time code{E.g. the path planning or human robot interaction. }
 Has a Gigabit Ethernet connector to communicate to the High-level PCs
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14. 4) COMMUNICATION
Each FPGA module has two ways to communicate.
1. Simple Ethernet controller
 Based on 10Mb/s 10BASE-T communication and UDP packets.
 Primarily used for debugging and to use the boards in a stand alone
situation.
2. High speed intercommunication
 FPGA fabric of central controller – Master & all FPGA modules - Slaves
 To chain the boards together and to connect them to the central controller
 EtherCAT, Powelink… ( High electronic complexity) @ 100Mb/s
 Direct pin–pin connection @1.05Gb/s-28.05Gb/s
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15. DISCUSSIONS AND EXPERIMENTAL RESULTS
A) HIGH PERFORMANCE MOTOR CONTROL
 Figure shows a torque controlled humanoid robot test platform
 To verify the performance of the High Current BLDC Controller
 Controls two high power PMSM motors(580 Watts) from
RoboDrive
 controller computed the desired current
 Low level motor controller produce the correct waveform by
using space vector modulation (SVM)
Space vector modulation (SVM) is an algorithm for
the control of pulse width modulation (PWM).
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16. B) Six DOFs Stereo Vision System
 High speed vision tracking system
 6 degrees of freedom 2 pan + 2 tilt + 2 torsion.
 Each eye is controlled by 3 piezo motors, to
control their position and velocity
 FPGA module receives desired angles alpha,
beta and gamma for each eye from the
central controller
 Angles are then converted into desired motor
positions and velocity using a Soft Core at
1khz
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17. C) Network
 A setup for testing and debugging the High speed communication
 Test for integrity
 send frames from the central controller to
FPGA modules
 Frame travels around the network and
returned to the central controller
 The central controller then checks the data
processed and that it does not have any
errors, as well as validates the returned data.
 Test for latency
 The time it takes to send a frame from the
central controller around the 3 modules with
150 bytes to each module and back.
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18. CONCLUSION
 FPGA module to fulfill the requirements to support the construction of humanoid
robots
 Only design the FPGA once and then using it on different boards
 On upgrading we only had to reconfigure the FPGA to communicate with the new
device
 Using FPGA,
1)High demanding control can be accomplished for the main humanoid limbs;
2)Multiple DoF can be controlled in parallel with a single FPGA module;
3)We can achieve high speed, low latency intercommunications for a network
of modules.
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