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4 Bit Counter




PRBS Generator




Accumulator
4 Bit counter

module count(Clock, Clear, out);

  input Clock, Clear;
  output [3:0] out;
         reg [3:0]out;
        always@(posedge Clock, negedge Clear)
        if((~Clear) || (out>=16))out=4'b 0000;
        else out=out+1;
endmodule

module Stimulus_v;

       reg Clock;
       reg Clear;
       wire [3:0] out;

       Count2Bit uut (
               .Clock(Clock),
               .Clear(Clear),
               .out(out)
       );
       initial
       begin
               $display("ttt 4 Bit Counter");
               $display("tt----------------------------------------");
               $display("ttClockttClearttOutput[4]");
               $display("tt----------------------------------------");
               $monitor("tt %btt %b tt %b ",Clock,Clear,out);
               #28 $display("tt----------------------------------------");
       end
       always
               #1 Clock=~Clock;
       initial
       begin
                 Clock=0;Clear=0;
               #10 Clear=1;
               #16Clear=0;
               #2 $stop;
 end

endmodule
PRBS Generator

 module prbsgen(clk, reset, en, q);
 input clk, reset, en;
 output [7:0] q;
           reg [7:0] q;
           always @(posedge clk or posedge reset)
           begin
   if (reset)
           q <= 8'd 1;
    else if (en)
           q <= {q[6:0], q[7] ^ q[5] ^ q[4] ^ q[3]};
   end
endmodule




 Accumulator

 module accumlator(Clk, CLR, D, Q);
        input Clk, CLR;
        input [3:0] D;
        output [7:0] Q;
        reg    [7:0] tmp;


 always @(posedge Clk or posedge CLR)
            begin
              if (CLR)
                tmp = 4'b0000;
              else
                tmp = tmp + D;
            end
           assign Q = tmp;

  endmodule

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VLSI Sequential Circuits II

  • 1. 4 Bit Counter PRBS Generator Accumulator
  • 2. 4 Bit counter module count(Clock, Clear, out); input Clock, Clear; output [3:0] out; reg [3:0]out; always@(posedge Clock, negedge Clear) if((~Clear) || (out>=16))out=4'b 0000; else out=out+1; endmodule module Stimulus_v; reg Clock; reg Clear; wire [3:0] out; Count2Bit uut ( .Clock(Clock), .Clear(Clear), .out(out) ); initial begin $display("ttt 4 Bit Counter"); $display("tt----------------------------------------"); $display("ttClockttClearttOutput[4]"); $display("tt----------------------------------------"); $monitor("tt %btt %b tt %b ",Clock,Clear,out); #28 $display("tt----------------------------------------"); end always #1 Clock=~Clock; initial begin Clock=0;Clear=0; #10 Clear=1; #16Clear=0; #2 $stop; end endmodule
  • 3. PRBS Generator module prbsgen(clk, reset, en, q); input clk, reset, en; output [7:0] q; reg [7:0] q; always @(posedge clk or posedge reset) begin if (reset) q <= 8'd 1; else if (en) q <= {q[6:0], q[7] ^ q[5] ^ q[4] ^ q[3]}; end endmodule Accumulator module accumlator(Clk, CLR, D, Q); input Clk, CLR; input [3:0] D; output [7:0] Q; reg [7:0] tmp; always @(posedge Clk or posedge CLR) begin if (CLR) tmp = 4'b0000; else tmp = tmp + D; end assign Q = tmp; endmodule