1. Jiang huihua
Birthday: Mar 1981 Cell: (65) 93801278
YiShun ST81, Singapore Email: jhhuu@hotmail.com
Jiang Huihua’s Resume
Objective:
R&D, Yield Enhancement, Process Integration, Quality department
Summary:
I have 10 years of experience in microelectronices/semiconductor industry
including process integration, improvement, yield enhancement and product
development, quality. Worked in singapore for 8 years. High volumn product
management / engineering expertise from NPI to End of Life (Product Lifecycle).
Holds a Master degree in Silicon Material and Singapore PR.
Areas of expertise include:
Semiconductor process
EEPROM device and Automotive device strategy (Subjected to TS16949 audit,
several automotive customer audit)
New product and process setup
Foundry outsourcing
Pareto/DOE/Cp&Cpk/SPC/APQP/FMEA
Parametric Test, EWS SBL/PPAT&GPAT.
Utilizing 8-D Process for Root Cause Anlysis and Problem Solving
Self-Evaluation:
Strong Analysis Skill, Dedicated, Proactive attitude, Cooperative
Work Experience:
04/2013---Present YE (Principal Engineer), (SG) Globalfoundries. Automotive
0.5um and 0.35um processs experience of EEProom (NVM). Role of team leader to
direct engineering group (4 engineers/1 technician) to enhance yield and process
robustness/margin/reliability.
07/2010---04/2013 YE (Senior Engineer), (SG) Globalfoundries. Automotive
0.5um Double and Single poly processs experience of EEProom (NVM).
Continously drive automotive product field return/0Km return ppm from 14plus
ppm to ~0.7ppm.
Product/Device Characterization: DOE on new process introduction to existing
process flow optimization and device characterizaion, margin check for better
process control.
Performed CD FEM/Overlay matrix for critical layers like Active/poly/tunnel
window/contact and Vt implant, gate/tunnel oxide thickness corner split for
leakage/Cg mapping/program time/cycling, retention characterization.
09/2007---07/2010 YE (Engineer), (SG) Chartered Semiconductor Manufacturing
Pte. LTE (Ex-Globalfoundries). Automotive 0.5um Double poly processs experience
of EEProom (NVM).
Real time manufacturing line support (high defectivity, critical CD/film thickness
OOS, fab pow trip and other excursion), WAT OOS or SPC/CPK(trend drift);
Continuosly mointoring and resolving issue of abnormal inline measurement
data /WAT(PCM,T84,ET) /CP(EWS) /SBL (Critical bins for chip performance –
leakage, device functional: Read after erase/program, data retention/cycling etc…)
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2. Jiang huihua
Birthday: Mar 1981 Cell: (65) 93801278
YiShun ST81, Singapore Email: jhhuu@hotmail.com
trend;
Fast response to low yield/reliability(Bondpad/Metal Corrosion, Poor adhesion
between metal and BPSG, slip line) issue and coordinate with engineer/production
team to minimize the impact (Shut down some tools or even the whole line for
process in charge as containment action of line excursion if need);
Proactively engage with automotive field return, failure analysis on root cause
finding with effective CA/PA
10/2005---09/2007 Process integration engineer (PIE), (Shanghai) Advanced
Semiconductor Manufacture Corp.(ASMC, founded by Philips). 2 years’ 0.35um
EEProom/Bicmos process experience.
Education Background:
09/2002---07/2005 Master in Silicon Material. Silicon Material State Key Lab,
Zhejiang University, China (ZJU). Research topic: Defect in Silicon Substrate
Point defects (COP, BMD, OSF, DZ & Dislocation Study) and Wafer strength Study;
Growth of p/p+ epitaxial silicon.
Article: “Growth of misfit dislocation-free p/p +
thick epitaxial silicon wafers on Ge-B-
codoped substrates”. Physica B: Physics of Condensed Matter, Volume 376, p. 841-844.
09/1998---07/2002 Degree in Material Engineering, ZJU.
Main achievement:
Good analysis skill & systematic problem solving skill - resolving issues like
Improved gate oxide breakdown automotive field return due to substrate COP
defect;
Continuously improved active, poly, cotact and metal, IMD, bondpad layer defects
(like galvanic corrosion) according to automotive field return FA pareto;
Active layer: HBR defects from pod contamination caused abnormal
oxide/poly/nitride film growth. Replace quartz boat by SiC to reduce furance
particle, Nitride thickness adjustment induced bird beak profile change and
increased decoder transistor breakdown to optimize cold test behavior;
Poly layer: Checker-board failure improved by introducing pre-wet at the
critical masking;
Contact layer: Solved contact to poly/active misalignment through optimizing
RTP tuning procedure to reduce thermal stress and tuning Oi to strengthen
substrate. It improved cold test margin and solved cell functional hard failure;
Metal layer: Long outstanding metal fish eye/metal & bondpad void defects;
Metal lifting due to poor TiN/BPSG adhesion and liquid spin force;
IMD layer: X-talk improved by IMD predictor formula optimization;
Bond pad loop: Megasonic clean alternate qualification.
Test programe optimization to screen out weak units:
Vpp optimization on periphery logic transistor and Zener Diode charge-pump;
Tighten leakage spec limit.
Skills:
Statistical analysis in yield enhancement
- Top failure bins pareto and bins vs yield correlation to find out key factor;
- Identifing good/bad groups through 3 sigma, 20-80 percentile method and
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3. Jiang huihua
Birthday: Mar 1981 Cell: (65) 93801278
YiShun ST81, Singapore Email: jhhuu@hotmail.com
failure mode/pattern/notch alignment signature;
- Commonality study for process, device, tool, recipe and hitrate study,
Waterfall time sequence analysis to zoom in affected timeframe,
Wait time and long process time to check abnormality;
- Correlation study on inline measurement data, WAT, yield, failure bin,
processing sequence, process change, fab activities;
- Mapping with tool/process configuration based on within wafer distribution
/wafer to wafer distribution and failure pattern;
- Find out process steps based on defect FA (SEM, EDX, Auger, SIMS, Optical
microscope, TEM, EELS, Dynamic Emmi, Liquid crystal)
Partition check and process short loop simulation to identify root cause
step.
Dig out WAT/EWS raw data for in-depth analysis:
- Benching WAT device or nano-probing on MOS transistor characterization
(Id_Vg for Vt, BVDS, Id_Vd family curve);
- Collaborate with product team to do more analysis based on provided within
wafer electrical raw data and distribution (leakage/Cg mapping/program time
etc), bitmap on failure die/chip.
8D with fish bone diagram & 5 why / FEMA or delta-FMEA methodology to reduce
automotive field return ppm level;
Others (Work with T-CAD team to do simulation, tapeout/reticle team, searching
paper/patent, experience sharing with colleague).
Language: English and Chinese
Software: MS Office;
Jmp, Siview, Promis, Mebes, Klarity Ace/Ace-XP, Oddsey, Datapower
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