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I3E Technologies

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Design of a low voltage low-dropout regulator
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An efficient constant multiplier architecture based on vertical horizontal binary common sub-expression elimination algorithm for reconfigurable fir filter synthesis
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Aging aware reliable multiplier design with adaptive hold logic
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A high performance fir filter architecture for fixed and reconfigurable applications
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A generalized algorithm and reconfigurable architecture for efficient and scalable orthogonal approximation of dct
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A combined sdc sdf architecture for normal i o pipelined radix-2 fft
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Reverse converter design via parallel prefix adders novel components, methodology,and implementations
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Pre encoded multipliers based on non-redundant radix-4 signed-digit encoding
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Energy optimized subthreshold vlsi logic family with unbalanced pull up down network and inverse narrow-width techniques
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Variable form carrier-based pwm for boost-voltage motor driver with a charge-pump circuit
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Ultrasparse ac link converters
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Single inductor dual-output buck–boost power factor correction converter
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Ripple minimization through harmonic elimination in asymmetric interleaved multiphase dc dc converters
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Resonance analysis and soft switching design of isolated boost converter with coupled inductors for vehicle inverter application
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Reliability evaluation of conventional and interleaved dc–dc boost converters
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